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Derive the state diagram, state table, state assignment table, and logic network using T flop-flops for...

Derive the state diagram, state table, state assignment table, and logic network using T flop-flops for the following circuit:

A FSM has input w and output z. The machine has to generate z=1 when the previous four values of w were 1001 or 1111; otherwise z=0. Overlapping patterns are allowed. An example of the desired behavior is:

w: 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0
z: 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1
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