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Without using Verilog, use D-type flip-flops and combinational logic to design a synchronous Moore finite-state machine...

Without using Verilog, use D-type flip-flops and combinational logic to design a synchronous Moore finite-state machine that monitors input A and asserts a binary output B if the sequence 101 is observed. For example:

A=010101101

B=000101001

---------------- time

a) Draw the state transition graph

b) Draw the encoded next state/output table

c) Determine the minimal circuit realization of the next state logic and output

d) Draw the circuit

e) Draw a timing diagram using the input sequence above showing the input, output, next state and current state.

Repeat the previous problem but instead design a Mealy finite-state machine.

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