Question

3. Parity generator [20]

• Submission file for this part: 3.circ
• Main circuit name: paritygen
• Input pin(s): inputw [1], sysclock [1]
• Output pin(s): outputq [1]

Derive a minimal state table for a Moore model FSM that acts as a three-bit parity generator. For every three bits that are observed on inputw during three consecutive clock cycles, the FSM generates the parity bit outputq = 1 if the number of 1s received in the sequence so far is odd. Thus, this is an even parity generator. Implement the FSM as a circuit in Logisim Evolution.

Note that the FSM outputs a 1 as long as the number of 1s received so far in the three-bit sequence is odd. This means that the circuit can output 1s before receiving all three bits. An example of this would be receiving the input 1 at the start; the circuit will output 1 after seeing the 1. Had the FSM received a 0 instead, the circuit would output 0. If the circuit receives a 0 after receiving the 1, the circuit would output 1 again. Note that after receiving the three bits, the circuit resets and starts looking at the next three bit set; thus, this is not a sliding window.

You may use a maximum of 3 flip flops for this problem. If you need to use more than 3 flip flops, your FSM is not minimized. You will lose a significant portion of credit if you have more than 3 flip flops in your circuit.

You may use a maximum of 14 AND gates and 4 OR gates with any number of inputs. You will lose a significant portion of credit if you have more, as it means your combinational logic is not minimized, or you made a mistake on code word assignment. If you violate both this and the previous constraint, you will get a 0.

Answer 1