Question

Write the Boolean equations and draw the logic diagram of the circuit whose outputs are defined by the following truth table:

(Please explain your process and how you use the K-map)

f1 | f2 | a | b | c |

1 | 1 | 0 | 0 | 0 |

0 | 1 | 0 | 0 | 1 |

1 | 0 | 0 | 1 | 0 |

1 | 1 | 0 | 1 | 1 |

1 | 0 | 1 | 0 | 0 |

0 | 1 | 1 | 0 | 1 |

1 | 0 | 1 | 1 | 1 |

W | X | Y | Z | F |

0 | 0 | 0 | 0 | 0 |

0 | 0 | 0 | 1 | 1 |

0 | 0 | 1 | 0 | 0 |

0 | 0 | 1 | 1 | 0 |

0 | 1 | 0 | 0 | 0 |

0 | 1 | 0 | 1 | 1 |

0 | 1 | 1 | 0 | 1 |

0 | 1 | 1 | 1 | 1 |

1 | 0 | 0 | 0 | 0 |

1 | 0 | 0 | 1 | 1 |

1 | 0 | 1 | 0 | 1 |

1 | 0 | 1 | 1 | 1 |

1 | 1 | 0 | 0 | 0 |

1 | 1 | 0 | 1 | 1 |

1 | 1 | 1 | 0 | 1 |

1 | 1 | 1 | 1 | 1 |

Answer #1

1) Implement the given logic function using a 4:1 MUX. (Ref: Lec
16, slide 5)
F(A,B,C) = Σm(0,1,3,7)
Show the truth table, the 4:1 MUX schematic with the inputs,
select inputs and the output.
2) For an 8:3 priority encoder:
a) Draw the schematic.
b) Write the truth table.
c) Write the Boolean expressions for each of the outputs in
terms of the inputs.
d) Draw the logic circuit for the outputs in terms of the
inputs.

digital logic
A digital circuit consists of four inputs and two outputs. One of the outputs takes the value
logical one "only when there is a majority of inputs to one". The other output is activated only if there is equal
number of inputs to one "than to zero".
a) Write the truth table.
b) Draw the necessary digital circuit with logic gates.
-----------------------------------------------------------------------------
A drip irrigation system has three sensors that measure different physical parameters. A
Sensor H measures...

Design a Single cell 1 bit Carry propagate (or Ripple Carry
Adder) full adder.
a. Generate the truth table
b. Using K-map or Boolean algebra, determine the logical
expression for Carry out (C-out) and Sum (S) Outputs
C. Draw the circuit diagram of the outputs in step b

Design a combinational circuit with 4 inputs (A, B, C, D) and
two outputs (F, G): The F output becomes ‘1’ when the corresponding
decimal value represented by the 4 input bits is divisible by 3
(for example, F=1 when input combination is 0011; as 0011is 3 in
decimal that is div. by 3). The G output becomes ‘1’ when the
corresponding decimal value represented by the 4 input bits is
divisible by 5.
Also, mention how many gate delays...

1. Given a Boolean function ?(?, ?, ?) such that ?(?, ?, ?) = 1
if the binary number ??? divides 36,
and ?(?, ?, ?) = 0 otherwise:
a. Construct the Truth Table for ?(?, ?, ?)
b. Find the Sum of Products (SoP) expansion for ?(?, ?, ?)
c. Minimize the SoP from above, using the K-map, state the
minimized function
d. Draw a combinatorial circuit for the minimized function

Question 1:A) A sequential circuit has two flip-flops A and B,
two inputs X and Y, and one output Z. The flip-flop input equations
and output function are as follows: SA = BX + B’Y’ RA = B’XY’ SB =
A’X RB = A + XY’ Z = AXY+BX’Y’ a) Draw the logic diagram of the
circuit. b) Derive the state table and state diagram of the
circuit.
Question 1: b)For the sequential circuits given below a) Write
flip-flop input...

Use the truth table to answer the
following questions, { X is Do not Care Condition}
A
B
C
D
Y
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
X
1
0
1
0
0
1
0
1
1...

Q.1.It is required to design an iterative
combinational circuit that computes the equation Z=2*X-3, where X
is an n-bit signed number in 2’s complement representation. (Hint:
-3 can be represented as -1+-1+-1 in 2’s complement representation,
where -1 is represented as 111…..111).
a)Determine the number of inputs and outputs
needed for your 1-bit cell. Explain the meaning of values in the
interface signals.
b)Derive the truth table of your 1-bit
cell.
c) Derive minimized equations for your 1-bit
using K-Map...

1) Provide a NAND circuit implementation for this function:
F(x,y,z) = xyz’ + x’y’z’ + xy’z’ + x’yz’ + xy’z + x’yz
2) A 3-bit parity check circuit will output a 1 for input having
even number of 1’s. Provide the truth table, Karnaugh map for the
minimized function, and circuit implementation using PLA.

Design an even parity detection circuit. A parity bit is an
error checking mechanism. Your circuit will count the number of 1’s
in a stream of bits. If the number of 1’s is even, the circuit
turns on an output called Y. Assume a single bit at each cycle –
call the input X. Do not use an accumulator or counter. Design the
even parity detection circuit using J-K flip-flops. Your answer
must include: a. The state diagram. b. The...

ADVERTISEMENT

Get Answers For Free

Most questions answered within 1 hours.

ADVERTISEMENT

asked 1 minute ago

asked 14 minutes ago

asked 20 minutes ago

asked 22 minutes ago

asked 23 minutes ago

asked 27 minutes ago

asked 29 minutes ago

asked 29 minutes ago

asked 38 minutes ago

asked 45 minutes ago

asked 46 minutes ago

asked 1 hour ago