Question

a) Draw the additional connections required for a 4-bit binary counter to go through the count sequence 5-to-14 then repeats using the Load signal. b) Write the Verilog-HDL that describes the behaviour of the counter of part a).

Answer 1

module counter_5to14 (
input clk, rst,
input [3:0] load_input,
output load,
output reg [3:0] count
);
wire load;
always @ (posedge clk)
begin
if (rst) // Synchronous active high reset
count <= 4'd5;
else
begin
if (load)
count <= 4'd5;
else
count <= count + 1'b1;
end
end
assign load = (count == 4'd14);
endmodule