Question

Design a 4 to 16 decoder using Verilog HDL.
The inputs are a four-bit vector W= [w1 w2 w3 w4] and an enable signal En. The outputs are
represented by the 16-bit vector Y= [y0 y1 …..y15].
a) Write Verilog HDL behavioral style code for 2-to-4 decoder.
b) Write Verilog HDL behavioral style code for 4-to-16 decoder by instantiation of 2-to-4
decoders.

Answer 1

a

module decoder2_4( 
input w1,w2, 
input En,
output reg y0,y1,y2,y3);
always @ (*)
begin
if (En==1)
case({w1,w2})
2'b00: begin y0=1;y1=0;y2=0;y3=0; end
2'b01: begin y0=0;y1=1;y2=0;y3=0; end
2'b10: begin y0=0;y1=0;y2=1;y3=0; end
2'b11: begin y0=0;y1=0;y2=0;y3=1; end
endcase
else
begin y0=0;y1=0;y2=0;y3=0; end
end

b

module decoder4_16(
input [1:4]w,
input En,
output [0:15]y);
wire e1,e2,e3,e4;

decoder2_4 x1(w[3],w[4],En,e1,e2,e3,e4);
decoder2_4 x2(w[1],w[2],e1,y[0],y[1],y[2],y[3]);
decoder2_4 x3(w[1],w[2],e2,y[4],y[5],y[6],y[7]);
decoder2_4 x4(w[1],w[2],e3,y[8],y[9],y[10],y[11]);
decoder2_4 x5(w[1],w[2],e4,y[12],y[13],y[14],y[15]);
endmodule