Question

A 4-Bit binary counter: A register containing 4 bits, all initialized to zero. The bits increment by 1 every 10 nanoseconds at each iteration until it gets to all ones in the 4-bit positions.

Write the Verilog code and testbench for the 4-bit binary counter.

Answer 1

Verilog code with testbench:

module counter_tb;



reg clk;

wire [3:0] y;



counter uut {

 .clk(clk);

.reset (reset);

.y (y);

};

initial begin

clk = 1; reset = 1; #100;

clk = 1; reset = 0; #100;



end

alwasy $10 clk = ~clk;

endmodule

Let me know if you have any doubts or if you need anything to change. 

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Thank You!
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