Question

Design a circuit for a synchronous 4-bit counter. Your counter
should count up starting from 0 to 9 (00002
to 10012)
and then wind back to 0 (00002)
–
after 9, it should go back to 0.
Use 4 JK flip-flops and any other gates you need. Include your
design documentation in your submission:

a.
Truth table

b.
Simplification (show your work)

2.
Build this circuit in
Logisim.
Please label each gate, including flip-flops. You may need the
following wiring components. To test your work, you may need to
turn on the Simulation
Enabled
and Tick
Enabled
(or manually poke CLK) options of the Simulate
menu. You can use the Tick
Frequency
setup of the Simulate
menu to adjust the frequency of the CLK

Answer #1

1) Truth table

2) Simplification

The J0 is simply identical as 1 , K0 also

The K1 and K3 have the same values by Q0

J1, J2, K2 simplification is very easy

3) Logisim

https://drive.google.com/file/d/1kBuFIQY3TFPv_OzOiLPLaX3UH8DI07Y4/view?usp=sharing

From this link, you can download the File.

Snippets

Enable ticking while working with the code

Regards,

Expert

All the best

Use JK Flip Flop to design a 2-bit synchronous counter (up
counter) that counts down as given: AB = 01, 11, 00, 10, and then
again 01. Show the design steps (e.g state table, j and k inputs
for k-maps etc) and draw the final circuit.

Design a 6-bit, shift-right register with D flip flops, and use
it to implement a circuit that detects the sequence “010010” (the
rightmost bit is the first arriving). Information shifts one
position right when a positiv edge of clk occurs The circuit has
the following inputs and outputs (use exactly these names for
inputs and outputs. Respect upper and lower case):
clk: Input. Clock signal.
RST: Reset signal. When RST = 1 flip flops are reset to 0.
IN: Data...

Design a counter which counts in the sequence that has
been assigned to you. Use D flip flops and NAND gates. Simulate
your design using SimUaid.
Submit the state table, D flip-flop input equations,
and transition graph determined in Part 6. The D flip-flop
equations can be derived using Karnaugh maps or using LogicAid by
entering a state table with zero input variables.
Sequence: 000,100,001,110,101,111,(repeat)
000,...
Also, please answer the following questions:
How can a D flip-flop be set to...

Design a 4-bit adder-subtractor circuit using the 4-bit binary
Full adders (74LS83) and any necessary additional logic gates. The
circuit has a mode input bit, M, that controls its operation.
Specifically, when M=0, the circuit becomes a 4-bit adder, and when
M=1, the circuit becomes a 4-bit subtractor that performs the
operation A plus the 2’s complement of B.Where A and B are two
4-bits binary numbers. That is,
* When M=0, we perform A+B, and we assume that
both...

3. Parity generator [20]
Submission file for this part: 3.circ
Main circuit name: paritygen
Input pin(s): inputw [1], sysclock [1]
Output pin(s): outputq [1]
Derive a minimal state table for a Moore model FSM that acts as
a three-bit parity generator. For every three bits that are
observed on inputw during three consecutive clock cycles,
the FSM generates the parity bit outputq = 1 if the number
of 1s received in the sequence so far is odd. Thus, this is...

ADVERTISEMENT

Get Answers For Free

Most questions answered within 1 hours.

ADVERTISEMENT

asked 1 minute ago

asked 3 minutes ago

asked 8 minutes ago

asked 10 minutes ago

asked 23 minutes ago

asked 33 minutes ago

asked 38 minutes ago

asked 38 minutes ago

asked 46 minutes ago

asked 1 hour ago

asked 1 hour ago

asked 1 hour ago