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Design a 4 to 16 decoder using Verilog HDL. The inputs are a four-bit vector W=...

Design a 4 to 16 decoder using Verilog HDL.

The inputs are a four-bit vector W= [w1 w2 w3 w4] and an enable signal En. The outputs are represented by the 16-bit vector Y= [y0 y1 …..y15].

a) Write Verilog HDL behavioral style code for 2-to-4 decoder.

b) Write Verilog HDL behavioral style code for 4-to-16 decoder by instantiation of 2-to-4 decoders.

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