Question

Simulate a D-Flip Flop on Xilinx using Verilog HDL | Behavioral Modelling

Answer 1

Simulate a D-Flip Flop on Xilinx using Verilog HDL | Behavioral Modelling:

module dp(d,db,pr,clr,clk,q,qb);
 input d;
 input db;
 input pr; 
input clr; 
input clk; 
output q; 
output qb; 
wire w1,w2,w3,w4,w5,w6; 
assign db=~(d); 
assign w1=~(d&qb&(~clk)); 
assign w2=~(db&q&(~clk)); 
assign w3=~(w1&pr&w4); 
assign w4=~(w2&clr&w3); 
assign w5=~(w3&clk); 
assign w6=~(w4& clk); 
assign q=~(w5&qb); 
assign qb=~(w6&q); 
endmodule

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