Question

- Examine the operation of the RS latch

- Examine the operation of the D flip-flop

- Examine the operation of the JK flip-flop

Please no handwritten answers

Answer 1

Examine the operation of the RS latch?

• A RS-flip-flop is that the simplest attainable memory part.
• It is built by feeding the outputs of 2 NOR gates back to the opposite NOR gates input.
• The inputs R and S area unit remarked because the Reset and Set inputs, severally.
• To perceive the operation of the RS-flip-flop (or RS-latch) contemplate the subsequent scenarios:
• S=1 and R=0: The output of very cheap NOR gate is up to zero, Q'=0.
• Hence each inputs to the highest NOR gate area unit up to one, thus, Q=1.
• Hence, the input combination S=1 and R=0 ends up in the flip-flop being set to Q=1.
• S=0 and R=1: almost like the arguments on top of, the outputs become Q=0 and Q'=1.
• We say that the flip-flop is reset.
• S=0 and R=0: Assume the flip-flop is ready (Q=0 and Q'=1), then the output of the highest NOR gate remains at Q=1 and therefore the bottom NOR gate stays at Q'=0.
• Similarly, once the flip-flop is in an exceedingly reset state (Q=1 and Q'=0), it'll stay there with this input combination.
• Therefore, with inputs S=0 and R=0, the flip-flop remains in its state.
• S=1 and R=1: This input combination should be avoided.

•             We will summarize the operation of the RS-flip-flop by the subsequent truth table.

R             S              Q             Q'            Comment

0              0              Q             Q'            Hold state

0              1              1              0              Set

1              0              0              1              Reset

1              1              ?              ?              Avoid

•             Note, the output letter of the alphabet' is solely the inverse of Q.

•             An RS flip-flop can even be made from NAND gate

Examine the operation of the D flip-flop?

The D flip-flop tracks the input, creating transitions with match those of the input D. The D stands for "data"; this flip-flop stores the worth that's on the information line. It will be thought of as a basic memory cell. A D flip-flop will be made of a set/reset flip-flop by attachment the set to the reset through associate degree electrical converter.

Examine the operation of the JK flip-flop?

Both the S and therefore the R inputs of the previous SR bistable have currently been replaced by 2 inputs known as the J and K inputs, severally when its artificer Jack Kilby. Then this equates to: J = S and K = R.

The 2 2-input AND gates of the gated SR bistable have currently been replaced by two 3-input NAND gates with the third input of every gate connected to the outputs at letter of the alphabet and letter of the alphabet. This cross coupling of the SR flip-flop permits the antecedently invalid condition of S = “1” and R = “1” state to be accustomed turn out a “toggle action” because the 2 inputs area unit currently interlocked.

If the circuit is currently “SET” the J input is pent-up by the “0” standing of letter of the alphabet through the lower NAND gate. If the circuit is “RESET” the K input is pent-up by the “0” standing of letter of the alphabet through the higher NAND gate. As letter of the alphabet and letter of the alphabet area unit perpetually totally different we are able to use them to regulate the input. once each inputs J and K area unit up to logic “1”, the JK flip flop toggles