Question

How do I design a divide by 4 clock in verilog using 2 D Flip Flop blocks? I have created this divide by 2 clock D Flip Flop block so far:

module divide_by_2(D, Clk,reset, Q, Qnext); //Divide by 2 clock with reset using D flip flop
   input Clk, D, reset;
   output Q,Qnext;
   reg Q;
  
   assign Qnext = ~Q;
  
   always @(posedge Clk or posedge reset) //always at the positive edge of the clock or reset
   begin
       if (reset)begin // asynchronous reset when reset is high
  
       Q <= 1'b0;; //Q gets the value 0
   end
  
       else begin
  
       Q <= D; // Q gets the value of D on posedge of clock
   end
  
   end
   endmodule

Also How would I design a divide by 5 clock using D Flip Flop blocks from this picture given?

Answer 1