Question

1. Write the equivalent gate level HDL for the code given below and Simulate it.

module example(w,x,y,z,a,b,c,d);

input a,b,c,d;

output w,x,y,z;

wire w,x,y,z;

assign w = (a&b)|(a&(~c)&(~d));

assign x = (~b&c)|(~b&d)|(b&(~c)&(~d));

assign y = c^d;

assign z = d;

endmodule

Answer 1

code:

output :

raw_code:

module example(w,x,y,z,a,b,c,d);
input a,b,c,d;
output w,x,y,z;
wire w,x,y,z;
wire bn,cn,dn;
wire m1,m2,m3,m4,m5; //declaring internal wire

not no1(bn,b); //negotiations of b,c,d
not no2(cn,c);
not no3(dn,d);

and a1(m1,a,b); //computing w
and a2(m2,a,cn,dn);
or o1(w,m1,m2);

and a3(m3,bn,c); //computing x
and a4(m4,bn,d);
and a5(m5,b,cn,dn);
or o2(x,m3,m4,m5);

xor x1(y,c,d); //computinig y

buf b1(z,d); //computing z

endmodule

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