Question

Use case statement to implement an 8:1 mutiplexer Verilog HDL module called mux8 with inputs s[2:0], D[7:0] and output Y.

write a testbench for the function.

Answer #1

Verilog HDL
Design a logic module to multiply an 8-bit binary number A [0:7]
by a 4-bit binary
number N [0:3]. The multiply is started when M is asserted. The
output F is asserted
when the multiply is completed and the product P [0: 15] is
available. The outputs need to
remain valid until the next multiply command is given. Assume M
is valid for several of
your clock cycles and then is de-asserted.
Implement the multiply using repeated addition...

(ii) Create a hierarchical Verilog 5-to-1 mux module with five
data inputs (a, b, c, d, e), three select inputs (s[2:0]), and one
output bit (f) using 4-to-1 multiplexers. Design the 4-to-1
multiplexer using behavioral code.

Analyze the following Verilog code and write down its
output as pictured in the code.
module blocking;
reg [0:7] A, B;
initial begin: init1
A = 3;
#1 A = A + 1; // blocking procedural assignment
B = A + 1;
$display("Output 1: A= %b B= %b", A, B );
A = 1;
#1 A <= A + 1;
B <= A + 1;
#1 $display ("Output 2: A= %b B= %b", A, B );
end
endmodul

1.) 2-bit binary numbers represent the values 0..3 with the
following encoding:
Encoding [1:0] Value
0 0 0
0 1 1
1 0 2
1 1 3
Develop the simplest Sum-of-Products equation possible that,
when given two 2-bit binary numbers X[1:0] and Y[1:0], will output
whether the value of X is greater than the value of Y.
2.) Assume that we have already implemented the solution to
problem #1 as a module “isGreater(F, X, Y)” in Verilog, and cannot
change...

1) Implement the given logic function using a 4:1 MUX. (Ref: Lec
16, slide 5)
F(A,B,C) = Σm(0,1,3,7)
Show the truth table, the 4:1 MUX schematic with the inputs,
select inputs and the output.
2) For an 8:3 priority encoder:
a) Draw the schematic.
b) Write the truth table.
c) Write the Boolean expressions for each of the outputs in
terms of the inputs.
d) Draw the logic circuit for the outputs in terms of the
inputs.

Using the programing language of Verilog I attempted to make a
counter to count from 0 to 9 then loop back to 0 using the internal
clock of the FPGA cyclone IV from altera. the code is posted at the
bottom counts from 0 to 1 then loop back to 0 instead of counting
up to 9. Can someone help me spot the error so it can count up to
9
module Encryption(SW, CLOCK_50, OUT, HEX0);
input[1:0]SW;
input CLOCK_50;
output...

Design a 6-bit, shift-right register with D flip flops, and use
it to implement a circuit that detects the sequence “010010” (the
rightmost bit is the first arriving). Information shifts one
position right when a positiv edge of clk occurs The circuit has
the following inputs and outputs (use exactly these names for
inputs and outputs. Respect upper and lower case):
clk: Input. Clock signal.
RST: Reset signal. When RST = 1 flip flops are reset to 0.
IN: Data...

1. write a truth table using this symbol: -->
2. write the inputs for the truth table to the left of the
--> and write the outputs for the truth table to the right of
the -->
3. write the compliment, or NOT using '
As an example:
The truth table for AND is written this way:
A B --> A AND B
0 0 --> 0
0 1 --> 0
1 0 --> 0
1 1 --> 1
or...

S = {<3, -2, 1, -4>, <2, 1, -2, -2>, <0, -7, 8,
-2>}
Determine whether b = < -4, 12, -12, 8 >
is in the span of S. Please write out the vector equation by
definition of span. Then convert the vector equation into system of
linear equations and matrix equation. No need to solve the
equation.

Q.1.It is required to design an iterative
combinational circuit that computes the equation Z=2*X-3, where X
is an n-bit signed number in 2’s complement representation. (Hint:
-3 can be represented as -1+-1+-1 in 2’s complement representation,
where -1 is represented as 111…..111).
a)Determine the number of inputs and outputs
needed for your 1-bit cell. Explain the meaning of values in the
interface signals.
b)Derive the truth table of your 1-bit
cell.
c) Derive minimized equations for your 1-bit
using K-Map...

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