Question

Problem 4 - 5 Pts] Verilog [Part 4.1 - 5 Pts] What does the Verilog code below do? Provide as much detail as possible and provide informative descriptions/labels for the 4 input/outputs.

module mystery (W, X, Y, Z);

input W, X, Y; output Z;

reg [7:0] P;

always @ (posedge W or posedge X)

begin

if (X) P = 8'b00000000;

else P = {P[6:0], Y);

end

assign Z = P[7];

endmodule

Answer 1

Here W and X acts as conditions to perform operation or not and Y as input to get assigned depending on X, W and Z is the output.