Question

The following Verilog module implements

module xyz(In,C,Out);

input In,C;

output Out;

wire x,y,In1,Out1;

nand n1 (x,In, C),

n2 (y,In1,C),

n3 (Out,x,Out1),

n4 (Out1,y,Out);

not nt (In1,In);

endmodule

a 2x1 multiplexor

b D latch

c D flip-flop

d RS flip-flop

e JK flip-flop

Answer 1

The following verilog module implements a D flip flop which needs four NAND Gates and one NOT gate for construction

module xyz(In,C,Out);

input In,C;

output Out;

wire x,y,In1,Out1;

nand n1 (x,In, C),

n2 (y,In1,C),

n3 (Out,x,Out1),

n4 (Out1,y,Out);

not nt (In1,In);

endmodule

A JK flip flop needs only four NAND Gates it doesn't require a NOT gate

RS FLIP Flop also needs four NAND gates

D latch uses two additional gates in front of the basic NAND-type RS-FLIP FLOP

A 2x1 mux doesn't require any not gate for it's construction

Hence option c) D flip-flop is the right answer