Question

Analyze the following Verilog code and write down its output as pictured in the code.
module blocking;
reg [0:7] A, B;
initial begin: init1
A = 1;
#1 A = A + 1; // blocking procedural assignment
B = A + 1;
$display("Output 1: A= %b B= %b", A, B );
A = 1;
#1 A <= A + 1;
B <= A + 1;
#1 $display ("Output 2: A= %b B= %b", A, B );
end
endmodule

Answer 1

module blocking // function blocking

reg[0:7] A,B // generates two arrays A and B of 8 elements

initial begin: init1 // begins the simulation

A = 1 // value of A is 00000001

#1 // 1ns delay

A=A+1 // adds 1 to A, So the value of A is 00000010

B=A+1 // adds 1 to A and stores it in B. So B is 00000011

$display("Output 1: A= %b B= %b", A, B );// prints the value of A and B

A=1 // value of A is 00000001

#1 // 1ns delay

A <= A + 1; //value of A is 00000010
B <= A + 1; // value of B is 00000010
#1 $display ("Output 2: A= %b B= %b", A, B ); //prints the value of A and B
end// end of simulation
The output is as follows:

Output 1: A= 00000010 B= 00000011
Output 2: A= 00000010 B= 00000010