Question

Analyze the following Verilog code and write down its output as
pictured in the code.

module blocking;

reg [0:7] A, B;

initial begin: init1

A = 1;

#1 A = A + 1; // blocking procedural assignment

B = A + 1;

$display("Output 1: A= %b B= %b", A, B );

A = 1;

#1 A <= A + 1;

B <= A + 1;

#1 $display ("Output 2: A= %b B= %b", A, B );

end

endmodule

Answer #1

module blocking // function blocking

reg[0:7] A,B // generates two arrays A and B of 8 elements

initial begin: init1 // begins the simulation

A = 1 // value of A is 00000001

#1 // 1ns delay

A=A+1 // adds 1 to A, So the value of A is 00000010

B=A+1 // adds 1 to A and stores it in B. So B is 00000011

$display("Output 1: A= %b B= %b", A, B );// prints the value of A and B

A=1 // value of A is 00000001

#1 // 1ns delay

A <= A + 1; //value of A is 00000010

B <= A + 1; // value of B is 00000010

#1 $display ("Output 2: A= %b B= %b", A, B ); //prints the value of
A and B

end// end of simulation

The output is as follows:

Output 1: A= 00000010 B= 00000011 Output 2: A= 00000010 B= 00000010

Analyze the following Verilog code and write down its
output as pictured in the code.
module blocking;
reg [0:7] A, B;
initial begin: init1
A = 3;
#1 A = A + 1; // blocking procedural assignment
B = A + 1;
$display("Output 1: A= %b B= %b", A, B );
A = 1;
#1 A <= A + 1;
B <= A + 1;
#1 $display ("Output 2: A= %b B= %b", A, B );
end
endmodul

Problem 4 - 5 Pts] Verilog [Part 4.1 - 5 Pts] What does the
Verilog code below do? Provide as much detail as possible and
provide informative descriptions/labels for the 4
input/outputs.
module mystery (W, X, Y, Z);
input W, X, Y; output Z;
reg [7:0] P;
always @ (posedge W or posedge X)
begin
if (X) P = 8'b00000000;
else P = {P[6:0], Y);
end
assign Z = P[7];
endmodule

Using the programing language of Verilog I attempted to make a
counter to count from 0 to 9 then loop back to 0 using the internal
clock of the FPGA cyclone IV from altera. the code is posted at the
bottom counts from 0 to 1 then loop back to 0 instead of counting
up to 9. Can someone help me spot the error so it can count up to
9
module Encryption(SW, CLOCK_50, OUT, HEX0);
input[1:0]SW;
input CLOCK_50;
output...

What will be the expected output of the following pseudo code?
Write exactly what would display when you execute the
statements.
Module main()
Declare Integer number
Display "Enter a number and I will display"
Input number
Call doubleNumber(number)
Display number
End Module
Module doubleNumber(Integer value)
Declare Integer result
Set result = value * 2
Display result
End Module

The following Verilog module implements
module xyz(In,C,Out);
input In,C;
output Out;
wire x,y,In1,Out1;
nand n1 (x,In, C),
n2 (y,In1,C),
n3 (Out,x,Out1),
n4 (Out1,y,Out);
not nt (In1,In);
endmodule
a 2x1 multiplexor
b D latch
c D flip-flop
d RS flip-flop
e JK flip-flop

How do I design a divide by 4 clock in verilog using 2 D Flip
Flop blocks? I have created this divide by 2 clock D Flip Flop
block so far:
module divide_by_2(D, Clk,reset, Q, Qnext); //Divide by 2 clock
with reset using D flip flop
input Clk, D, reset;
output Q,Qnext;
reg Q;
assign Qnext = ~Q;
always @(posedge Clk or posedge reset) //always at the
positive edge of the clock or...

Use case statement to implement an 8:1 mutiplexer Verilog HDL
module called mux8 with inputs s[2:0], D[7:0] and output Y.
write a testbench for the function.

Design a module that can perform a binary-coded decimal
(BCD) addition. You have two 4-bit BCD (decimal digits 0 to 9)
inputs “a” and “b” and an 8-bit output “x” which represents a two
digit BCD number.
X [7:4] represents the upper BCD digits
X [3:0] represents the lower BCD digits
In the Verilog file, please code a BCD adder. It should
follow the following format.
module bcd_adder( a,b,x );
input wire [3:0] a;
input wire [3:0] b;
output reg...

(ii) Create a hierarchical Verilog 5-to-1 mux module with five
data inputs (a, b, c, d, e), three select inputs (s[2:0]), and one
output bit (f) using 4-to-1 multiplexers. Design the 4-to-1
multiplexer using behavioral code.

Analyze the following programs and write down the output of the
program. Please print every character (including whitespace
character) clearly!
# include <iostream>
using namespace std;
int fun( int a )
{
int b = a * 2;
return b;
}
int main()
{
int y = 5;
cout << fun(y)
<< endl;
cout << fun(-- y)
<< endl;
cout << fun(y--)
<< endl;
cout << y
<<endl;
return 0;
}

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