Question

As an alternative to using a SPDT switch and an RS latch to debounce a switch signal,
would passing the bouncing signal thru a D flip-flop remove bounces? What constraint might you place on a D type flip-flop’s clock to mitigate the possibility of passing a bounce thru?
(Consider your past experience with bouncing switches).

Answer 1

We can use a latch or an SR flip-flop to eliminate signal bounce or noise caused by the switching of a mechanical device (switches, buttons etc.). When the switch occurs, only one input is affected immediately before stabilizing. This is followed by the second input bouncing before the contact stabilizes. Both inputs are never bouncing at the same time so the output of the latch will never change due to signal bounce. Directly below is a schematic for a latch de-bouncing circuit.

We can use D flip-flop to remove bounces by simply passing the signal through D flip-flop.

From the truth table of D flip-flop if we apply "POSITIVE EDGE TRIGGERING" clock then the output will be same as input. i.e. it mitigate the possibility of passing a bouncing through.