Question

1) Implement the given logic function using a 4:1 MUX. (Ref: Lec 16, slide 5)

F(A,B,C) = Σm(0,1,3,7)

Show the truth table, the 4:1 MUX schematic with the inputs, select inputs and the output.

2) For an 8:3 priority encoder:

a) Draw the schematic.

b) Write the truth table.

c) Write the Boolean expressions for each of the outputs in terms of the inputs.

d) Draw the logic circuit for the outputs in terms of the inputs.

Answer #1

1. Implement the given logic function using a 4:1 MUX. F(A,B,C)
= Σm(0,1,3,7)
Show the truth table, the 4:1 MUX schematic with the inputs,
select inputs and the output.
2. For an 8:3 priority encoder:
a) Draw the schematic.
b) Write the truth table.
c) Write the Boolean expressions for each of the outputs in
terms of the inputs.
d) Draw the logic circuit for the outputs in terms of the
inputs.

digital logic
A digital circuit consists of four inputs and two outputs. One of the outputs takes the value
logical one "only when there is a majority of inputs to one". The other output is activated only if there is equal
number of inputs to one "than to zero".
a) Write the truth table.
b) Draw the necessary digital circuit with logic gates.
-----------------------------------------------------------------------------
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(a) Implement the following Boolean function F using the
two-level forms: AND-NOR and
OR-NAND , F = B'D'+ AC'D'+ACD+A'CD'
(b) Convert the above problem into standard POS, expression using
the truth table and minimize
using K-map.
(c) Design a combinational circuit with four inputs and one output.
The Algebraic expression
must be minimized using K-MAP. The output must be one for the
digits which are present in
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represented by ABCDE is ODD and 0 otherwise. A is the MSB and E is
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Draw the function F(A,B,C,D,E,F) and show the work that led you
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Since I am not so sadistic as to have you draw
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(for example, F=1 when input combination is 0011; as 0011is 3 in
decimal that is div. by 3). The G output becomes ‘1’ when the
corresponding decimal value represented by the 4 input bits is
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Also, mention how many gate delays...

Logic Circuit
Problem #3
Given the following logic function: F(a,b,c,d) = ?
m(0,3,7,9,11,13,15)+?d(4,6,8) use a Karnaugh Map to, a) Find a
minimal SOP expression Answer: F(a,b,c,d) = b) Find a minimal POS
expression
Answer: F(a,b,c,d) =
Problem #4
Implement the function F(a,b,c,d) given in problem #3 using two
3-to-8 decoders, both active low enabled and active low output.
F(a,b,c,d) = ? m(0,3,7,9,11,13,15)+?d(4,6,8)
Answer:
Problem #5
Implement the function in the previous problem: F(a,b,c,d) = ?
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Hardware security
HW-1
Combinational Logic
Q.1 a) Complete the truth table for the 4-inputs, 16 cells LUT (
Look-up Table) and map the follwing function on the LUT. Asume ‘a’
to the MSB ( Most significant bit) and lable all inputs and outputs
of the LUT.
F= a+bd
LUT
A
(MSB)
B
C
D
(LSB)
F
(output)
Draw the circuit level for the above function.
Q.2 Assume that a simple diagram of a
switch used in SRAM based FPGA...

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the key B belongs to the master (the name of the head is B) and the
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For table shown in figure 1 construct (a) a Boolean expression
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