Question

(a) Implement the following Boolean function F using the
two-level forms: AND-NOR and

OR-NAND , F = B'D'+ AC'D'+ACD+A'CD'

(b) Convert the above problem into standard POS, expression using
the truth table and minimize

using K-map.

(c) Design a combinational circuit with four inputs and one output.
The Algebraic expression

must be minimized using K-MAP. The output must be one for the
digits which are present in

your Roll Number Digits. Any duplications must be avoided.

Answer #1

Please find the answer below

(3) Use K-map to simplify the following expressions, and
implement them with two-level NAND gate circuits:
(a) F(A,B,C,D)=A’B’C+AC’+ACD+ACD’+A’B’D’
(b) F(A,B,C)=(A’+B’+C’)(A’+B’)(A’+C’)

In addition to NAND and NOR, find four more two-input boolean
functions that are each individually universal. Give a logic
expression for each of your functions, using AND, OR, and NOT, and
prove that each of these functions is individually universal, by
showing for example that you can implement AND, OR, and NOT with
your function. You may use the constant values zero and one as
inputs to your universal functions to implement other functions.
Name your functions f1, f2,...

1) Provide a NAND circuit implementation for this function:
F(x,y,z) = xyz’ + x’y’z’ + xy’z’ + x’yz’ + xy’z + x’yz
2) A 3-bit parity check circuit will output a 1 for input having
even number of 1’s. Provide the truth table, Karnaugh map for the
minimized function, and circuit implementation using PLA.

1) Implement the given logic function using a 4:1 MUX. (Ref: Lec
16, slide 5)
F(A,B,C) = Σm(0,1,3,7)
Show the truth table, the 4:1 MUX schematic with the inputs,
select inputs and the output.
2) For an 8:3 priority encoder:
a) Draw the schematic.
b) Write the truth table.
c) Write the Boolean expressions for each of the outputs in
terms of the inputs.
d) Draw the logic circuit for the outputs in terms of the
inputs.

Logic Circuit
Problem #3
Given the following logic function: F(a,b,c,d) = ?
m(0,3,7,9,11,13,15)+?d(4,6,8) use a Karnaugh Map to, a) Find a
minimal SOP expression Answer: F(a,b,c,d) = b) Find a minimal POS
expression
Answer: F(a,b,c,d) =
Problem #4
Implement the function F(a,b,c,d) given in problem #3 using two
3-to-8 decoders, both active low enabled and active low output.
F(a,b,c,d) = ? m(0,3,7,9,11,13,15)+?d(4,6,8)
Answer:
Problem #5
Implement the function in the previous problem: F(a,b,c,d) = ?
m(0,3,7,9,11,13,15)+?d(4,6,8), using a single 4...

Using K-map to simplify the following Boolean function:
F(A,B,C,D) = m(1,3,5,6,7,9,11,12,13,15)

Using K-map to simplify the following Boolean function:
F(A,B,C,D) = å
m(1,3,5,6,7,9,11,12,13,15)

VIVA QUESTIONS: 1. Implement the following function using VHDL
coding. (Try to minimize if you can). F(A,B,C,D)=(A'+B+C).
(A+B'+D'). (B+C'+D') . (A+B+C+D) 2. What will be the no. of rows in
the truth table of N variables? 3. What are the advantages of VHDL?
4. Design Ex-OR gate using behavioral model? 5. Implement the
following function using VHDL code f=AB+CD. 6. What are the
differences between half adder and full adder? 7. What are the
advantages of minimizing the logical expressions?...

Design a combinational circuit with 4 inputs (A, B, C, D) and
two outputs (F, G): The F output becomes ‘1’ when the corresponding
decimal value represented by the 4 input bits is divisible by 3
(for example, F=1 when input combination is 0011; as 0011is 3 in
decimal that is div. by 3). The G output becomes ‘1’ when the
corresponding decimal value represented by the 4 input bits is
divisible by 5.
Also, mention how many gate delays...

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