Question

1. Implement the given logic function using a 4:1 MUX. F(A,B,C) = Σm(0,1,3,7)

Show the truth table, the 4:1 MUX schematic with the inputs, select inputs and the output.

2. For an 8:3 priority encoder:

a) Draw the schematic.

b) Write the truth table.

c) Write the Boolean expressions for each of the outputs in terms of the inputs.

d) Draw the logic circuit for the outputs in terms of the inputs.

Answer #1

The truth table, schematic and output expression of 4:1 MUX are shown below.

Truth table of given function F:

K-map implementation of the given funtion F:

From K-map, we obtain

Since , [Following rule of Boolean algebra]

F can be implemented using a 4:1 MUX as follows:

Here S_{1} = A, S_{0} = B, D_{0} = 1,
D_{1} = C, D_{2} = 0, D_{3} = C

1) Implement the given logic function using a 4:1 MUX. (Ref: Lec
16, slide 5)
F(A,B,C) = Σm(0,1,3,7)
Show the truth table, the 4:1 MUX schematic with the inputs,
select inputs and the output.
2) For an 8:3 priority encoder:
a) Draw the schematic.
b) Write the truth table.
c) Write the Boolean expressions for each of the outputs in
terms of the inputs.
d) Draw the logic circuit for the outputs in terms of the
inputs.

(a) Implement the following Boolean function F using the
two-level forms: AND-NOR and
OR-NAND , F = B'D'+ AC'D'+ACD+A'CD'
(b) Convert the above problem into standard POS, expression using
the truth table and minimize
using K-map.
(c) Design a combinational circuit with four inputs and one output.
The Algebraic expression
must be minimized using K-MAP. The output must be one for the
digits which are present in
your Roll Number Digits. Any duplications must be avoided.

#9) You are to implement the following function
F(A,B,C,D,E,F) which outputs a 1 whenever the binary number
represented by ABCDE is ODD and 0 otherwise. A is the MSB and E is
the LSB.
Draw the function F(A,B,C,D,E,F) and show the work that led you
to that answer.
Since I am not so sadistic as to have you draw
the truth table of a 6 variable function and draw the K-map of such
a function, you should realize, as a...

digital logic
A digital circuit consists of four inputs and two outputs. One of the outputs takes the value
logical one "only when there is a majority of inputs to one". The other output is activated only if there is equal
number of inputs to one "than to zero".
a) Write the truth table.
b) Draw the necessary digital circuit with logic gates.
-----------------------------------------------------------------------------
A drip irrigation system has three sensors that measure different physical parameters. A
Sensor H measures...

please answer the following questions!!!!
1. Draw the truth table and block diagram for a 2:4 decoder. Use
positive logic inputs and a negative logic (also reffered to as an
active low or inverted) enable line and negative logic outputs 2.
Design a circuit to implement the 2: decoder block diagram in
question 1 using only NAND gates and inverters.
4. Use a 4:1 multiplexer and a minimum number of exterel gates
to implement a solution to F(0,3,4,7,10)
5. Use...

Logic Circuit
Problem #3
Given the following logic function: F(a,b,c,d) = ?
m(0,3,7,9,11,13,15)+?d(4,6,8) use a Karnaugh Map to, a) Find a
minimal SOP expression Answer: F(a,b,c,d) = b) Find a minimal POS
expression
Answer: F(a,b,c,d) =
Problem #4
Implement the function F(a,b,c,d) given in problem #3 using two
3-to-8 decoders, both active low enabled and active low output.
F(a,b,c,d) = ? m(0,3,7,9,11,13,15)+?d(4,6,8)
Answer:
Problem #5
Implement the function in the previous problem: F(a,b,c,d) = ?
m(0,3,7,9,11,13,15)+?d(4,6,8), using a single 4...

Design a combinational circuit with 4 inputs (A, B, C, D) and
two outputs (F, G): The F output becomes ‘1’ when the corresponding
decimal value represented by the 4 input bits is divisible by 3
(for example, F=1 when input combination is 0011; as 0011is 3 in
decimal that is div. by 3). The G output becomes ‘1’ when the
corresponding decimal value represented by the 4 input bits is
divisible by 5.
Also, mention how many gate delays...

VIVA QUESTIONS: 1. Implement the following function using VHDL
coding. (Try to minimize if you can). F(A,B,C,D)=(A'+B+C).
(A+B'+D'). (B+C'+D') . (A+B+C+D) 2. What will be the no. of rows in
the truth table of N variables? 3. What are the advantages of VHDL?
4. Design Ex-OR gate using behavioral model? 5. Implement the
following function using VHDL code f=AB+CD. 6. What are the
differences between half adder and full adder? 7. What are the
advantages of minimizing the logical expressions?...

Hardware security
HW-1
Combinational Logic
Q.1 a) Complete the truth table for the 4-inputs, 16 cells LUT (
Look-up Table) and map the follwing function on the LUT. Asume ‘a’
to the MSB ( Most significant bit) and lable all inputs and outputs
of the LUT.
F= a+bd
LUT
A
(MSB)
B
C
D
(LSB)
F
(output)
Draw the circuit level for the above function.
Q.2 Assume that a simple diagram of a
switch used in SRAM based FPGA...

A
switching circuit has three inputs
(A, B, C) and one
output
(Z).
If
A= 0, the
output Z is the exclusive-OR of B and C. If
A = 1, the
output is the equivalence of
B and C.
A.
Find the
truth table for Z.
B.
Write
the
minterm expansion
for Z in decimal form and in terms of A, B, C.
C.
Write
the
maxterm expansion
for Z in decimal form and in terms of A, B, C....

ADVERTISEMENT

Get Answers For Free

Most questions answered within 1 hours.

ADVERTISEMENT

asked 1 minute ago

asked 9 minutes ago

asked 58 minutes ago

asked 1 hour ago

asked 1 hour ago

asked 1 hour ago

asked 1 hour ago

asked 1 hour ago

asked 1 hour ago

asked 2 hours ago

asked 2 hours ago

asked 2 hours ago