Question

The following code runs on a microprocessor with five pipelined stages. In the code lw is...

The following code runs on a microprocessor with five pipelined stages. In the code lw is a load word and sw is a store word. The register on the far right is the target register for lw and add and source for sw. The memory latency is 2 cycles.

lw 0(r1),r2

label1:    beq r2,r0,label2 # not taken once, then taken

lw 0(r2),r3

beq r3,r0,label1 # taken

add r1,r3,r1

label2: sw 0(r2),r1

Identify all the possible hazards that may exist in the execution of the previous code. Indicate the name of the hazard and what instructions are involved in it.

Engineering   Computer-Science   
0 0
Add a commentTranscribed image text
Next >

Homework Answers

Answer #1

answer to above question

0 0
Know the answer?
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Log In

Sign Up

Not the answer you're looking for?
Ask your own homework help question
Similar Questions
Consider the following MIPS code and a 5 stages processor as discussed in class, and assume...
Consider the following MIPS code and a 5 stages processor as discussed in class, and assume the loop executes 3 times: loop: lw r1,4(r7) lw r2,8(r7) lw r3,12(r7) add r1,r1, r3 sw r1,4(r7) bne r1,r2,loop addi r1,r1,42 c. Draw the execution diagram. (10 points) d. The CPI (cycles per instruction) is obtained by computing the ratio of total cycles to number of instructions. Compute the CPI for the for the pipeline on this code. (5 points)
Consider a program having following sequence of instructions, where the syntax consists of an opcode followed...
Consider a program having following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers: Instruction no Instructions 1 ADD R3, R1, R2 2 LOAD R6, [R3] 3 AND R7, R5, 3 4 ADD R1, R6, R0 5 SUB R2, R1, R6 6 AND R3, R7, 15 7 SUB R5, R3, R4 8 ADD R0, R1, R10 9 LOAD R6, [R5] 10 SRL R7, R0, 8 Assume the...
1. Read the following set of instructions, and answer questions. add r5, r2, r1 lw r3,...
1. Read the following set of instructions, and answer questions. add r5, r2, r1 lw r3, 4(r5) or r3 , r5, r3 sw r3 , 0(r5) add r2, r5, r1 b. Assume there are no forwarding, show the result in multiple-cycle diagram.
(20pts each) Read the following set of instructions, and answer questions. add     r5, r2, r1 lw...
(20pts each) Read the following set of instructions, and answer questions. add     r5, r2, r1 lw      r3, 4(r5) or      r3, r5, r3 sw      r3, 0(r5) add     r2, r5, r1 Assume there are no forwarding, try reorganize the order of these instructions such that these 5 instructions can be finished sooner. Insert stall cycles only when reordering does not help. Note that reordering instructions should not cause any incorrect value being write into registers. Show the reordered 5...
Suppose a MIPS processor uses the simple 5-stage pipeline described in the text, where the stages...
Suppose a MIPS processor uses the simple 5-stage pipeline described in the text, where the stages are instruction fetch, instruction decode and operand fetch, execute and calculate address, memory access, and register write. Suppose further that • There is a single memory for both instruction and data, which can only support one read or write each cycle. • There is no “forwarding” in the pipeline. Thus, if an instruction B relies on a value written into a register by an...
What are the values of the registers, as decimal integers, after executing the following code? mov...
What are the values of the registers, as decimal integers, after executing the following code? mov r0, #9 mov r1, #1 top: cmp r0, #0 beq finish lsl r1, r1, #1 sub r0, r0, #1 b top finish: mov r2, #47 R0:  R1:  R2:  R3:
Consider executing the following code on the pipelined datapath that we discussed in class. a). During...
Consider executing the following code on the pipelined datapath that we discussed in class. a). During the 5th cycle, which registers are being read and which register(s) will be written (using the register file)? b). Explain what the forwarding unit is doing during the 5th cycle of execution. Which registers are being compared? List all pairs of registers that are compared during the 5th cycle for the forwarding unit. (First, you need to determine which instruction's values are in the...
(MIPS Assembly Language): Assume the following piece of MIPS code: label1: .text 0x4000fc lui $t0, 1022...
(MIPS Assembly Language): Assume the following piece of MIPS code: label1: .text 0x4000fc lui $t0, 1022 ori $t0, $t0, 2048 srl $t1, $t0, 18 sw $t0, 101($t1) slti $t2, $t1, 5 beq $t2, $0, label3 label2:... ... label3:... a) The code modifies a word in memory at the following address (circle one): (i) 1022 (ii) 101 (iii) 5 (iv) 10220000 (v) Other (provide your own answer): _________________ b) The following value is stored in memory (circle one): (i) 0x17 (ii)...
Given the following sequential list of VEX operations: A. add $r3 = $r1, $r2 B. sub...
Given the following sequential list of VEX operations: A. add $r3 = $r1, $r2 B. sub $r8 = $r1, $r3 C. sub $r7 = $r1, 2 D. add $r1 = $r1, 1 E. mpy $r6 = $r3, $r2 Which VEX operations can be scheduled simultaneously to make up the second VLIW instruction? The constructed schedule should satisfy the following conditions: Assume infinite resources and no limit to the number of operations scheduled to a single instruction. Operations that are scheduled...
Consider the following code segment, where the branch is taken 30% of the time and not-taken...
Consider the following code segment, where the branch is taken 30% of the time and not-taken 70% of the time. R1 = R2 + R3 R4 = R5 + R6 R7 = R8 + R9 if R10 = 0, branch to linex R11 = R12 + R13 R14 = R11 + R15 R16 = R14 + R17 ... linex: R18 = R19 + R20 R21 = R18 + R22 R23 = R18 + R21 ... Consider a 10-stage in-order processor,...
ADVERTISEMENT
Need Online Homework Help?

Get Answers For Free
Most questions answered within 1 hours.

Ask a Question
ADVERTISEMENT