Question

The following code runs on a microprocessor with five pipelined stages. In the code lw is a load word and sw is a store word. The register on the far right is the target register for lw and add and source for sw. The memory latency is 2 cycles.

lw 0(r1),r2

label1:    beq r2,r0,label2 # not taken once, then taken

lw 0(r2),r3

beq r3,r0,label1 # taken

add r1,r3,r1

label2: sw 0(r2),r1

Identify all the possible hazards that may exist in the execution of the previous code. Indicate the name of the hazard and what instructions are involved in it.

Answer 1

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