Question

Suppose a MIPS processor uses the simple 5-stage pipeline described in the text, where the stages are instruction fetch, instruction decode and operand fetch, execute and calculate address, memory access, and register write. Suppose further that

• There is a single memory for both instruction and data, which can only support one read or write each cycle.

• There is no “forwarding” in the pipeline. Thus, if an instruction B relies on a value written into a register by an instruction A, then the execute stage for B cannot proceed until the register write stage for A has completed.

• In the absence of hazards, a new instruction can be fed to the pipeline every cycle.

Consider the following MIPS code.

            Lw $s1, 0($s2)

            Lw $s3, 12($s4)

            Add $s5,$s1,$s3

            Beq $s5,$s5, L1

            Sw $s5,0($s3)

      L1: Sw $s5,12($s4)

1.   Show all hazards?

2. Fill in the schedule below showing exactly where each step of all instructions is executed.

Answer 1

Note: Assuming "Fill in the schedule below showing exactly where each step of all instructions is executed." means creating a pipeline diagram. Please let me know if you have questions.

Pipeline Diagram

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

lw $s1, 0($s2)

IF

ID

EX

M

RW

lw $s3, 12($s4)

IF

ID

EX

M

RW

add $s5,$s1,$s3

IF

ID

EX

M*

RW

Wait for RW of previous instr

beq $s5,$s5, L1

IF

ID

EX

M*

RW*

IF cannot occur in same cycle as M

sw $s5,0($s3)

Not Executed

L1: sw $s5,12($s4)

IF

ID

EX

M

RW*

Wait for EX of branch

* -> Stages do not use memory and registers

The code takes 15 cycles to complete