Question

Consider a program having following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers:

Instruction no	Instructions
1	ADD R3, R1, R2
2	LOAD R6, [R3]
3	AND R7, R5, 3
4	ADD R1, R6, R0
5	SUB R2, R1, R6
6	AND R3, R7, 15
7	SUB R5, R3, R4
8	ADD R0, R1, R10
9	LOAD R6, [R5]
10	SRL R7, R0, 8

Assume the use of a four-stage pipeline: fetch, decode/issue, execute, write back. Assume that all pipeline stages take one clock cycle except for the execute stage. For simple integer arithmetic and logical instructions, the execute stage takes one cycle, but for a LOAD from memory, Six cycles are consumed in the execute stage. If we have a simple scalar pipeline that allows only In-order Issue and In-order execution, Show the execution of the program in time steps.

Answer 1

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