Question

1) Provide a NAND circuit implementation for this function: F(x,y,z) = xyz’ + x’y’z’ + xy’z’ + x’yz’ + xy’z + x’yz

2) A 3-bit parity check circuit will output a 1 for input having even number of 1’s. Provide the truth table, Karnaugh map for the minimized function, and circuit implementation using PLA.

Answer #1

**SOLUTION-**

**1)**

**2)**

If I apply K map on this there will be 3 groups

output F = Z' + X'Y+YX'

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