Question

Q.1.It is required to design an iterative combinational circuit that computes the equation Z=2*X-3, where X is an n-bit signed number in 2’s complement representation. (Hint: -3 can be represented as -1+-1+-1 in 2’s complement representation, where -1 is represented as 111…..111).

a)Determine the number of inputs and outputs needed for your 1-bit cell. Explain the meaning of values in the interface signals.

b)Derive the truth table of your 1-bit cell.

c) Derive minimized equations for your 1-bit using K-Map method.

d)Write a Verilog model for modeling your 1-bit cell by using an assign statement for each output.

e)Write a Verilog model for modeling a 4-bit circuit based on the 1-bit model you have.

f) Write a Verilog test bench to test the correctness of your design for the following input values: {X=-2}, {X=-1}, {X=0}, {X=1}, {X=2}, {X=3}, {X=4} and {X=5}.

Answer 1

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