Question

Design an even parity detection circuit. A parity bit is an error checking mechanism. Your circuit will count the number of 1’s in a stream of bits. If the number of 1’s is even, the circuit turns on an output called Y. Assume a single bit at each cycle – call the input X. Do not use an accumulator or counter. Design the even parity detection circuit using J-K flip-flops. Your answer must include: a. The state diagram. b. The state table. c. Simplified equations – use either Boolean algebra or k-maps. d. The final circuit(s).

Answer 1

The State Diagram

The State Table

State Assignment

Since there are three states, we can use two flip flops. So the sates are assigned as

The Design Table

The design table is filled by assigning the values to the state table. And then filling the J and K values required using the excitation table of JK fillip flop

Now lets draw the K map for

The output will be high when the state is S2. So the output will be

So the circuit diagram will be