Question

Consider the following hypothetical microprocessor. Assume this processor uses a 32-bit address and 32-bit data bus....

Consider the following hypothetical microprocessor. Assume this processor uses a 32-bit address and 32-bit data bus. What is the memory capacity when connected to a 16-bit memory? Show your work and give your final answer in Bytes.

Homework Answers

Answer #1

//do comment if further clarification needed

Assuming byte addressable scheme

Given processor has 32 bit address bus

So max memory supported = 232 bytes = 4294967296 bytes

But the connected memory has only 16 bits for address

So, memory capacity = 216 bytes = 65536

If Processor is word addressable

then word size = 32 bits = 4 bytes

This means that 4 bytes can fit into 1 memory location

Then for connected memory of 16 bits

memory capacity = 216 x 4 bytes = 262144 bytes

Know the answer?
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for?
Ask your own homework help question
Similar Questions
Consider the following hypothetical microprocessor. Assume this processor uses a 32-bit address and 32-bit data bus....
Consider the following hypothetical microprocessor. Assume this processor uses a 32-bit address and 32-bit data bus. Consider a 4-bit I/O port number. How many 8-bit I/O ports can be supported?
consider a hypotehtical microprocessor generating a 32-bit address ( for example, assume the program counter and...
consider a hypotehtical microprocessor generating a 32-bit address ( for example, assume the program counter and the address registers are 320bits wide) and having a 32-bit data bus. What is the maximum memory address space that the processor can access directly if it connected to a 16-bit memory
Consider a hypothetical microprocessor having 64-bit instructions composed of two fields: the first two bytes contain...
Consider a hypothetical microprocessor having 64-bit instructions composed of two fields: the first two bytes contain the opcode and the remainder the immediate operand or operand address. Discuss the impact on the system if the speed of the microprocessor bus has a 64-bit local address bus and a 32-bit local data bus.
Consider the following two hypothetical microprocessors A and B. Microprocessor A has an 8-bit external data...
Consider the following two hypothetical microprocessors A and B. Microprocessor A has an 8-bit external data bus whereas microprocessor B has a 16-bit external data bus. Other than that difference, these processors are identical including bus cycle speed. Answer the following two questions. Consider that all instructions and operands are two Bytes. Assume 100 transfers of operands and instructions, each of which are two Bytes long. By what factor do the maximum data transfer rates vary between A and B?...
Consider a hypothetical microprocessor having 64-bit instructions composed of two fields: the first two bytes contain...
Consider a hypothetical microprocessor having 64-bit instructions composed of two fields: the first two bytes contain the opcode and the remainder the immediate operand or operand address. What is the maximum directly accessible memory capacity (in Bytes)? Provider answer in Giga Bytes.
consider a 64bit microprocessor with a 32-bit external databus, driven by a 120-mhz input clock. assume...
consider a 64bit microprocessor with a 32-bit external databus, driven by a 120-mhz input clock. assume that this microprocessor has a bus cycle whose minimum duration equals three input clock cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain in bytes
Suppose a 32-bit microprocessor has a 16-bit data bus running on a 12 MHz clock. A....
Suppose a 32-bit microprocessor has a 16-bit data bus running on a 12 MHz clock. A. If the minimum duration of a bus cycle is 6 clock cycles, what is the maximum data transfer rate? B. If the memory in A needs to wait 2 clock cycles for each data access, what is the maximum data transfer rate? C. How does the maximum data transfer rate change when the frequency of the bus is doubled to improve performance in A?...
consider two microprocessors having 32-bit and 640bit wide external data busses, respectfully the two processors are...
consider two microprocessors having 32-bit and 640bit wide external data busses, respectfully the two processors are identical otherwise and their bus cycles are the same speed. Suppose all instructions and operands are four bytes. By what factor do the maximum data transfer rates vary A: The 64-bit microprocessor is twice as fast B: The 320bit microprocessor is twice as fast C: The 64-bit microprocessor is four times faster D: The 32-bit microprocessor is four times faster E: Neither microprocessor is...
1. The memory units that follow are specified by the number of words times the number...
1. The memory units that follow are specified by the number of words times the number of bits per word. How many address lines and input/output data lines are needed in each case? (a) 8K X 16 (b) 2G X 8 (c) 16M X 32 (d) 256K X 64 2. Give the number of bytes stored in each memory unit in question 1. 3. Word number 563 decimal in the memory shown in Fig. 7.3 (see Mano-Ch7.pdf) contains the binary...
A computer system has 16 processing registers R0,···,R15, where each register has 32-bit storage capacity. The...
A computer system has 16 processing registers R0,···,R15, where each register has 32-bit storage capacity. The computer system uses a common bus system for data transfer between registers, memory and ALU. Answer the following questions if common bus is designed using multiplexers Size of each MUX needed for the design Number of MUXs needed Size of the bus (in bits)