Question

A computer system has 16 processing registers R0,···,R15, where each register has 32-bit storage capacity. The...

A computer system has 16 processing registers R0,···,R15, where each register has 32-bit storage capacity. The computer system uses a common bus system for data transfer between registers, memory and ALU. Answer the following questions if common bus is designed using multiplexers

  1. Size of each MUX needed for the design
  2. Number of MUXs needed
  3. Size of the bus (in bits)

Homework Answers

Answer #1

Number of MUX needed= Number of bits in the register.

As here we have 32 registers so we need 32 MUX.

And the size of the MUX = 16 X 1

Size of the BUS= Number of registers= 16

I'm giving you a small example below with 4, 4-bit registers.

Know the answer?
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for?
Ask your own homework help question
Similar Questions
Memory organization: For a memory consisting of 32 modules, each with a capacity of 1M x8...
Memory organization: For a memory consisting of 32 modules, each with a capacity of 1M x8 bits (here a basic memory storage unit is a byte or 8 bits), how many bits are needed to represent each address that is uniquely associated with each basic storage unit? For this memory system, if high-order interleaving is used, what is the address structure (i.e., what bits are used to select the chip and what bits are used to identify the offset within...
A 2-address computer has 65 instructions, 32 Registers, 4MB memory, and three flags negative, zero,  and positive...
A 2-address computer has 65 instructions, 32 Registers, 4MB memory, and three flags negative, zero,  and positive (N, Z, P). Assume length of each instruction is 32 bits. Find a format for BR instruction
Suppose a 32-bit microprocessor has a 16-bit data bus running on a 12 MHz clock. A....
Suppose a 32-bit microprocessor has a 16-bit data bus running on a 12 MHz clock. A. If the minimum duration of a bus cycle is 6 clock cycles, what is the maximum data transfer rate? B. If the memory in A needs to wait 2 clock cycles for each data access, what is the maximum data transfer rate? C. How does the maximum data transfer rate change when the frequency of the bus is doubled to improve performance in A?...
1. The memory units that follow are specified by the number of words times the number...
1. The memory units that follow are specified by the number of words times the number of bits per word. How many address lines and input/output data lines are needed in each case? (a) 8K X 16 (b) 2G X 8 (c) 16M X 32 (d) 256K X 64 2. Give the number of bytes stored in each memory unit in question 1. 3. Word number 563 decimal in the memory shown in Fig. 7.3 (see Mano-Ch7.pdf) contains the binary...