Question

Suppose a 32-bit microprocessor has a 16-bit data bus running on a 12 MHz clock.

A. If the minimum duration of a bus cycle is 6 clock cycles, what is the maximum data transfer rate?
B. If the memory in A needs to wait 2 clock cycles for each data access, what is the maximum data transfer rate?
C. How does the maximum data transfer rate change when the frequency of the bus is doubled to improve performance in A?
D. In A, how does the maximum data transfer rate change if you double the width of the data bus?

Answer 1

With a 32-bit local address bus and a 16-bit local data bus, it would take 2 cycles to fetch the 32 bit instruction. A 16-bit local address bus would slow down operation due to only being able to pass half the instruction a cycle. With a 32-bit local address bus and a 16-bit local data bus, it would take 2 cycles to fetch the 32 bit instruction. A 16-bit local address bus would slow down operation due to only being able to pass half the instruction a cycle.