Question

Make a stimulus for BCD to 7-segment decoder in verilog.

Answer 1

Answer:-----------BCD to 7-segment decoder in Verilog-------------------->

The BCD to 7 Segment Decoder converts 4 bit binary to 7 bit control signal which can be displayed on 7 segment display. Seven display consist of 7 led segments to display 0 to 9 and A to G.

BCD to 7 segment display Decoder Truth Table:--------

B3 B2 B1 B0	A B C D E F G
0 0 0 0	0 0 0 0 0 0 1
0 0 0 1	1 0 0 1 1 1 1
0 0 1 0	0 0 1 0 0 1 0
0 0 1 1	0 0 0 0 1 1 0
0 1 0 0	1 0 0 1 1 0 0
0 1 0 1	0 1 0 0 1 0 0
0 1 1 0	0 1 0 0 0 0 0
0 1 1 1	0 0 0 1 1 1 1
1 0 0 0	0 0 0 0 0 0 0
1 0 0 1	0 0 0 0 1 0 0

The boolean expression for the logic circuit is

A = B0 + B2 + B1B3 + B1’B3′

B = B1′ + B2’B3′ + B2B3

C = B1 + B2′ + B3

D = B1’B3′ + B2B3′ + B1B2’B3 + B1’B2 + B0

E = B1’B3′ + B2B3′

F = B0 + B2’B3′ + B1B2′ + B1B3′

G = B0 + B1B2′ + B1’B2 + B2B3′

Verilog Code:-------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bcd_7seg is
Port ( B0,B1,B2,B3 : in STD_LOGIC;
A,B,C,D,E,F,G : out STD_LOGIC);
end bcd_7seg;
architecture Behavioral of bcd_7seg is
begin
A <= B0 OR B2 OR (B1 AND B3) OR (NOT B1 AND NOT B3);
B <= (NOT B1) OR (NOT B2 AND NOT B3) OR (B2 AND B3);
C <= B1 OR NOT B2 OR B3;
D <= (NOT B1 AND NOT B3) OR (B2 AND NOT B3) OR (B1 AND NOT B2 AND B3) OR (NOT B1 AND B2) OR B0;
E <= (NOT B1 AND NOT B3) OR (B2 AND NOT B3);
F <= B0 OR (NOT B2 AND NOT B3) OR (B1 AND NOT B2) OR (B1 AND NOT B3);
G <= B0 OR (B1 AND NOT B2) OR ( NOT B1 AND B2) OR (B2 AND NOT B3);
end Behavioral;