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Write verilog code for Huffman Decoder with testbench.

Write verilog code for Huffman Decoder with testbench.
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Answer #1

module residue5_huffman(input clk, rst, input[1:0] x, output[2:0] out);

reg[2:0] n_state, p_state;

parameter Zero = 3'b000, One = 3'b001, Two = 3'b010,

Three = 3'b011, Four = 3'b100;

always@(p_state, x) begin

n_state = Zero;

case(p_state)

Zero:…n_state = …

One:… n_state = …

Two:… n_state = …

Three:… n_state = …

Four:… n_state = …

default:…

endcase

end// Combinational part

always@(posedge clk, posedge rst) begin

if(rst)

p_state = Zero;

else

p_state = n_state;

end// Register part

assign out = p_state;

endmodule

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