Question

Trying to make a seven segment driver on vivado using verilog. I have all 7 components module coded some as logical gates some as decoders and muxs. they all tested and workout. When I implement them i get an error [HDL 9-3756] overwriting previous definition of module 'schematic1'. All seven modules I want to make them all into one module they all share same 4 bit binary input different outputs. How do i make these seven modules into one acting module?

Answer 1

Create main module

1. Then instantiate all sub modules into the main module.

2 make sure that when you instantiating the sub modules the order of the netlist variables in the module is same . This is an important point to remember while instantiating