Question

Write a HDLcode for an 8 bit shift register with a reset pin. for system verilog please

Answer 1

module shift_register (
   input logic Clock, // Clock input
   input logic Reset, // Reset input
   input logic Load, // Load = 1 then In1 is loaded into shift register
   input logic [7:0] In1, // Input to be loaded when Load = 1
   output logic Out1 // Out1
);

logic [7:0] reg1;

always_ff @(posedge Clock)
  begin
   if (Reset == 1'b1) // Active high synchronous reset
   reg1 <= 8'b0;
   else if (Load == 1'b1)
   reg1 <= In1;
   else
   reg1 <= {1'b0, reg1[7:1]};
  end

assign Out1 = reg1[0];

endmodule