Question

Model 74LS164- an 8-Bit Serial In/Parallel Out Shift Register using behavioral style using VHDL, create a test bench to apply various stimulus to it, and demonstrate its functionality for various test cases through simulated waveform and configuration on the DE2-115 target board.

Answer 1

--VHDL Model

library ieee;
use ieee.std_logic_1164.all;

entity ic74LS164 is
   port (   CP   : in std_logic;
       A, B   : in std_logic;
       MR   : in std_logic;
       QA   : out std_logic;
       QB   : out std_logic;
       QC   : out std_logic;
       QD   : out std_logic;
       QE   : out std_logic;
       QF   : out std_logic;
       QG   : out std_logic;
       QH   : out std_logic
   );
end ic74LS164;

architecture behavioral of ic74LS164 is

signal reg : std_logic_vector(0 to 7);

signal AB : std_logic_vector (1 downto 0);

begin
  
   AB   <= (A & B);

   process (CP, MR)
   begin
       if (MR = '0') then
           reg <= (others => '0');
       else
           if (CP = '1' and CP'event) then
               case AB is
                   when "01"=> reg <= '0' & reg(0 to 6);
                   when "10"=> reg <= '0' & reg(0 to 6);
                   when "11"=> reg <= '1' & reg(0 to 6);
                   when others=> null;
               end case;
           end if;
       end if;
   end process;

QA <= reg(0);
QB <= reg(1);
QC <= reg(2);
QD <= reg(3);
QE <= reg(4);
QF <= reg(5);
QG <= reg(6);
QH <= reg(7);

end behavioral;

--------------------------------------------------------------------------------------------------------------------------------------------------------------------

--Testbench

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity ic74LS164_tb is
end;

architecture bench of ic74LS164_tb is

component ic74LS164
   port (   CP   : in std_logic;
       A, B   : in std_logic;
       MR   : in std_logic;
       QA   : out std_logic;
       QB   : out std_logic;
       QC   : out std_logic;
       QD   : out std_logic;
       QE   : out std_logic;
       QF   : out std_logic;
       QG   : out std_logic;
       QH   : out std_logic
   );
end component;

signal CP: std_logic;
signal A, B: std_logic;
signal MR: std_logic;
signal QA: std_logic;
signal QB: std_logic;
signal QC: std_logic;
signal QD: std_logic;
signal QE: std_logic;
signal QF: std_logic;
signal QG: std_logic;
signal QH: std_logic ;

constant clock_period: time := 10 ns;
  

begin

uut: ic74LS164 port map ( CP => CP,
A => A,
B => B,
MR => MR,
QA => QA,
QB => QB,
QC => QC,
QD => QD,
QE => QE,
QF => QF,
QG => QG,
QH => QH );

stimulus: process
begin

   MR <= '0';
   wait for 2*clock_period;

   MR <= '1';
  
   A <= '1';
   B <= '1';
   wait for 8*clock_period;

   A <= '0';
   B <= '1';
   wait for 2*clock_period;

   A <= '1';
   B <= '0';
   wait for 2*clock_period;
  
   A <= '0';
   B <= '0';
   wait for 2*clock_period;

wait;
end process;

clocking: process
begin
   CP <= '0';
   wait for clock_period/2;
   CP <= '1';
   wait for clock_period/2;
end process;

end;

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------