Question

Write a VHDL code for a 4-bit shift register that shifts from right to left.

Answer 1

The VHDL code is

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shiftreg is
port(   clk,x: in std_logic;     --x is the input signal inserted at the left side
        Q: out std_logic_vector(3 downto 0));          
end shiftreg;
architecture Behavioral of shiftreg is
signal S:std_logic_vector(3 downto 0);
begin
process(x,clk)
begin
S<="0000";
if(clk'event and clk='1')then
S<=S(2 downto 0)&x;
end if;
end process;
Q<=S;
end Behavioral;

(rotate operation is diffrent from shifting operation)

(If you have any query leave a comment, Thank you)