Please write verilog code for a 4-bit Carry Look-Ahead (CLA) Adder.
Code for 4 bit CLA
module CLA(a,b,ci,co,s);
input [3:0]a,b;
output [4:0]s;
input ci;
output co;
wire [3:0]G,P,C;
assign G = a&b;
assign P = a^b;
assign co=G[3]+ (P[3]&G[2]) + (P[3]&P[2]&G[1]) +
(P[3]&P[2]&P[1]&G[0]) +
(P[3]&P[2]&P[1]&P[0]&ci);
assign C[3]=G[2] + (P[2]&G[1]) + (P[2]&P[1]&G[0]) +
(P[2]&P[1]&P[0]&ci);
assign C[2]=G[1] + (P[1]&G[0]) + (P[1]&P[0]&ci);
assign C[1]=G[0] + (P[0]&ci);
assign C[0]=ci;
assign s = {co,P^C};
endmodule
Code for
Test Bench
module fi;
reg [3:0] a;
reg [3:0] b;
reg ci;
wire co;
wire [4:0] s;
CLA uut (
.a(a),
.b(b),
.ci(ci),
.co(co),
.s(s)
);
initial begin
// Initialize Inputs
a = 4'b1101;
b = 4'b1011;
ci = 0;
end
endmodule.
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