Assume that each of PG Unite, Carry Look ahead (CLA) Unit and
Sum unit has a delay of2delta, what will be the Delay of:
1- 128-bit adder if for design complexity reasons, the size of each
CLA is limited to 4-bits.
2- 256 -bit adder if for design complexity reasons, the size of each CLA is limited to 8-bits.
Show one equation that represent each level of dealy, example PG unit, first level CLA ( show C0) etc.
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