Question

Memory Hierarchy & Caches Based on the following behavior, which of the following block sizes is...

Memory Hierarchy & Caches

Based on the following behavior, which of the following block sizes is NOT possible for our cache?

Consider:

1) Cache starts empty, also known as a cold cache

2) Access (address: hit/miss) stream: (14: miss), (15: hit), (16: miss)

Addresses above are in decimal

a. 4 bytes

b. 8 bytes

c. 16 bytes

d. 32 bytes

Homework Answers

Answer #1

Let's evaluate each case one by one :

a. 4 bytes

In this case, following groups of physical addresses will be mapped together in corresponding blocks :

  • 0, 1, 2, 3
  • 4, 5, 6, 7
  • 8, 9, 10, 11
  • 12, 13, 14, 15
  • 16, 17, 18, 19
  • 20, 21, 22, 23
  • 24, 25, 26, 27
  • 28, 29, 30, 31

So if accesses are :

  • 14 => miss
    • Block for (12, 13, 14, 15) is loaded.
  • 15 => hit
    • Due to (12, 13, 14, 15) already loaded.
  • 16 => miss
    • Block for (16, 17, 18, 19) is loaded.

So, access-sequence possible = YES

b. 8 bytes

In this case, following groups of physical addresses will be mapped together in corresponding blocks :

  • 0, 1, 2, 3, 4, 5, 6, 7
  • 8, 9, 10, 11, 12, 13, 14, 15
  • 16, 17, 18, 19, 20, 21, 22, 23
  • 24, 25, 26, 27, 28, 29, 30, 31

So if accesses are :

  • 14 => miss
    • Block for (8, 9, 10, 11, 12, 13, 14, 15) is loaded.
  • 15 => hit
    • Due to (8, 9, 10, 11, 12, 13, 14, 15) already loaded.
  • 16 => miss
    • Block for (16, 17, 18, 19, 20, 21, 22, 23) is loaded.

So, access-sequence possible = YES

c. 16 bytes

In this case, following groups of physical addresses will be mapped together in corresponding blocks :

  • 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
  • 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31

So if accesses are :

  • 14 => miss
    • Block for (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) is loaded.
  • 15 => hit
    • Due to (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) already loaded.
  • 16 => miss
    • Block for (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31) is loaded.

So, access-sequence possible = YES

d. 32 bytes

In this case, following groups of physical addresses will be mapped together in corresponding blocks :

  • 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31

So if accesses are :

  • 14 => miss
    • Block for (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31) is loaded.
  • 15 => hit
    • Due to (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31) already loaded.
  • 16 => miss
    • not possible, as address 16 is already present in the cache (in the solitary block).

So, access-sequence possible = NO

So, the correct option is

d. 32 bytes

Know the answer?
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for?
Ask your own homework help question
Similar Questions
Assume a byte-addressable memory has 64K bytes. Blocks are 8 bytes in length and the cache...
Assume a byte-addressable memory has 64K bytes. Blocks are 8 bytes in length and the cache consists of 4K bytes. Show the format for a main memory address assuming a 4-way set associative cache mapping scheme. Include the field names as well as their sizes. A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main...
Consider a cache of 4 lines of 16 bytes each. Main memory is divided into blocks...
Consider a cache of 4 lines of 16 bytes each. Main memory is divided into blocks of 16 bytes each. That is, block 0 has bytes with addresses 0 through 15, and so on. Now consider a program that accesses memory in the following sequence of addresses: Once: 63 through 70. Loop two times: 15 through 32; 80 through 95. Suppose the cache is organized as two-​way set associative, with two sets of two lines each. Even-​numbered blocks are assigned...
Consider the following memory hierarchy. Unit Access Latency Local Miss Rate ----------------------------------------------------------------------- L1 1.5 cycles 80%...
Consider the following memory hierarchy. Unit Access Latency Local Miss Rate ----------------------------------------------------------------------- L1 1.5 cycles 80% L2 15 cycles 65% Memory 150 cycles 100% What is the average memory access time? (Hint: AMAT= hit time + miss rate * miss penalty)
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of 32-byte size, with direct-map (S = 1) placement policy and LRU replacement policy, answer each of the following questions: Determine the address fields for index, tag and block offset in the memory address. How many sets are there in the cache? How many blocks in the main memory are mapped to the same set of blocks in cache? If associative (parallel) comparison is to...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of 32-byte size, with direct-map (S = 2) placement policy and LRU replacement policy, answer each of the following questions: Determine the address fields for index, tag and block offset in the memory address. How many sets are there in the cache? How many blocks in the main memory are mapped to the same set of blocks in cache? If associative (parallel) comparison is to...
Consider one direct mapped cache with four sectors holding one block per sector and one 32-bit...
Consider one direct mapped cache with four sectors holding one block per sector and one 32-bit word per block. The machine is byte addressed on word boundaries and uses write allocation with write back. For each of the following cache accesses, is it a hit or miss? If it is a miss, identify the type of miss (compulsory, capacity, or conflict miss). Assume the cache starts out completely invalidated. read 0x00 read 0x04 write 0x08 read 0x10 read 0x08 write...
1. Given a Memory Bus interface from processor to DRAM main memory that takes the following...
1. Given a Memory Bus interface from processor to DRAM main memory that takes the following number of cycles. 3 memory bus clock cycle to send the address 20 memory bus clock cycles for each DRAM access initiated 1 memory bus clock cycle to send a word of data Sought: find the number of clock cycles required to transfer a complete block of 4 words from memory to the cache, for each of the following designs Part 1: the interface...
14. For a direct-mapped cache with a 32-bit address and 32-bit words, the following address bits...
14. For a direct-mapped cache with a 32-bit address and 32-bit words, the following address bits are used to access the cache. Tag Index Offset 31-16 15-5 4-0 What is the cache block size (in words)? How many blocks does the cache have?
1. The memory units that follow are specified by the number of words times the number...
1. The memory units that follow are specified by the number of words times the number of bits per word. How many address lines and input/output data lines are needed in each case? (a) 8K X 16 (b) 2G X 8 (c) 16M X 32 (d) 256K X 64 2. Give the number of bytes stored in each memory unit in question 1. 3. Word number 563 decimal in the memory shown in Fig. 7.3 (see Mano-Ch7.pdf) contains the binary...
1.) Perform the following multiplication using Booth’s algorithm: (You will receive full credit only if you...
1.) Perform the following multiplication using Booth’s algorithm: (You will receive full credit only if you show all your work)      13 x -13 (a) 27/4 Using paper pencil approach and (b) simulate how a machine does this job 2.)Perform the following division as directed: (a) 27/4 using non-restoring division algorithm // we need 4 quotient bits. (b) Using Newton-Raphson algorithm find 1/d when d=0.84 // show the results of the first 3 iterations 3.) A real-time computer system has...