Question

1. Given a Memory Bus interface from processor to DRAM main memory that takes the following number of cycles.

3 memory bus clock cycle to send the address

20 memory bus clock cycles for each DRAM access initiated

1 memory bus clock cycle to send a word of data

Sought: find the number of clock cycles required to transfer a complete block of 4 words from memory to the cache, for each of the following designs

Part 1: the interface between main memory and cache is one word wide

1. 80
2. 87
3. 96
4. 65
5. 43

Part 2: the interface between main memory and cache is 4 words wide( and access is un-interleaved)

6. 28
7. 32
8. 27
9. 24
10. 34

Answer 1

Solution

Explanation

Part 1

the interface between main memory and cache is one word wide
=3+20*4+4
=3+80+4
=87 cycles.

Part 2

the interface between main memory and cache is 4 words wide( and access is un-interleaved)

=3+20+1
=24 cycles

--

all the best