Question

In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of 32-byte size, with direct-map (S = 2) placement policy and LRU replacement policy, answer each of the following questions:

1. Determine the address fields for index, tag and block offset in the memory address.
2. How many sets are there in the cache?
3. How many blocks in the main memory are mapped to the same set of blocks in cache?
4. If associative (parallel) comparison is to be performed with all tags for identification, how many XOR gates are required?
5. Determine the hit ratio in running each of the following program segments (each instruction occupies a word):
   1. m a sequence of 100 consecutive instructions starting from address x148 with each instruction executed once in order
   2. a loop of 32 consecutive instructions starting at location x148 and is iterated 20 times
   3. a loop of 64 consecutive instructions starting at location x148 and is iterated 20 times

Answer 1

B.

Total # of block inside cache = Cache size / Block size

=128/32 = 4

Therefore total number of set = 4/2 = 2

A.

Since total of set inside cache = 2

Number of index bits = log 2 = 1 bit

Block offset = log (Block size) = log 32 = 5 bits

Memory bits= log 1024 = 10 bits

Tag bits = 10 - 1 - 5 = 4 bits

C.

Total # of block in main memory = 1024/32 = 32

Now since we have 2 set, number of block mapped to one set is 32/2 = 16

D. In fully associative mapping, number of tag bits = 5 since index bits = 0.

So # of XOR gate required = # of tag bits = 5

Please don't post so many questions at once. Only one question or 4 sub question at a time is what we have been asked to solve . If you have any questions comment down and please? upvote thanks