Question

14. For a direct-mapped cache with a 32-bit address and 32-bit words, the following address bits...

14. For a direct-mapped cache with a 32-bit address and 32-bit words, the following address bits are used to access the cache.

Tag

Index

Offset

31-16

15-5

4-0

    1. What is the cache block size (in words)?
    1. How many blocks does the cache have?

Homework Answers

Answer #1

Q-> 14. For a direct-mapped cache with a 32-bit address and 32-bit words, the following address bits are used to access the cache.

Tag

Index

Offset

31-16

15-5

4-0

1) What is the cache block size (in words)?

as. offset field is from 0 to 4, ie 4 bits

=> block size of cache = 24 = 16 words

.

2) How many blocks does the cache have?

as index field is from 5 to 15,

=> no of bits for index = 10

=> no of blocks = 210 = 1024 blocks

Know the answer?
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for?
Ask your own homework help question
Similar Questions
1. Suppose we have a 32KB direct-mapped data cache with 32-byte blocks. a) Show how a...
1. Suppose we have a 32KB direct-mapped data cache with 32-byte blocks. a) Show how a 32-bit memory address is divided into tag, index and offset. Show clearly how many bits are in each field. b) How many total bits are there in this cache? 2. Suppose we have a 8KB direct-mapped data cache with 64-byte blocks. a) Show how a 32-bit memory address is divided into tag, index and offset. Show clearly how many bits are in each field....
13. Calculate the total number of bits required to implement a 1024 KiB direct-mapped cache with...
13. Calculate the total number of bits required to implement a 1024 KiB direct-mapped cache with 10-word blocks. Assume that the cache is byte addressable, and addresses and data words are both 32 bits. (1 KiB = 210 bytes)
The cache is direct mapped, 16 lines, each line is 2 bytes The offset field is...
The cache is direct mapped, 16 lines, each line is 2 bytes The offset field is ________ bits The line field is ________ bits The tag field is ________ bits line tag byte 0 byte 1 (can someone explain this to me) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a...
Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a cache of 128 blocks, where each cache block contains 8 bytes. For four-way set associative cache, to which block of cache the address 0x1895BA maps? Group of answer choices Block 70 Block 16 Block 23 Not enough information
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of 32-byte size, with direct-map (S = 1) placement policy and LRU replacement policy, answer each of the following questions: Determine the address fields for index, tag and block offset in the memory address. How many sets are there in the cache? How many blocks in the main memory are mapped to the same set of blocks in cache? If associative (parallel) comparison is to...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of...
In a hypothetical system with 1024 bytes of main memory, 128 bytes of cache, blocks of 32-byte size, with direct-map (S = 2) placement policy and LRU replacement policy, answer each of the following questions: Determine the address fields for index, tag and block offset in the memory address. How many sets are there in the cache? How many blocks in the main memory are mapped to the same set of blocks in cache? If associative (parallel) comparison is to...
Consider one direct mapped cache with four sectors holding one block per sector and one 32-bit...
Consider one direct mapped cache with four sectors holding one block per sector and one 32-bit word per block. The machine is byte addressed on word boundaries and uses write allocation with write back. For each of the following cache accesses, is it a hit or miss? If it is a miss, identify the type of miss (compulsory, capacity, or conflict miss). Assume the cache starts out completely invalidated. read 0x00 read 0x04 write 0x08 read 0x10 read 0x08 write...
SRAM with 4k words of 32 bits each. How many address bits are needed to address...
SRAM with 4k words of 32 bits each. How many address bits are needed to address these words? 1. Assuming that the central memory array has the same number of rows as it has columns, how many rows are there? 2.How many of address bits are used by the row decoder 3.How many words are stored in each row 4. How many are used by column decoder
1a) A memory unit has 28-bit address lines and 64-bit input/output data lines. How many bytes...
1a) A memory unit has 28-bit address lines and 64-bit input/output data lines. How many bytes of data can this memory hold? How many words does it contain, and how large is each word? b) A memory unit consists of 32M words of 16-bit each. How many bits wide address lines and input-output data lines are needed to access this memory? c) A memory unit consists of 512K bytes of data. How many bits wide address lines are needed to...
1. The memory units that follow are specified by the number of words times the number...
1. The memory units that follow are specified by the number of words times the number of bits per word. How many address lines and input/output data lines are needed in each case? (a) 8K X 16 (b) 2G X 8 (c) 16M X 32 (d) 256K X 64 2. Give the number of bytes stored in each memory unit in question 1. 3. Word number 563 decimal in the memory shown in Fig. 7.3 (see Mano-Ch7.pdf) contains the binary...
ADVERTISEMENT
Need Online Homework Help?

Get Answers For Free
Most questions answered within 1 hours.

Ask a Question
ADVERTISEMENT