Question

VERILOG

Design an Arithmetic Logic Unit (ALU) that can perform four-bit
1. Four-bit addition;
2. Four-bit subtraction;
3. Four-bit multiplication;
4. Four-bit comparator (that compares two binary numbers to check whether two numbers are equal, or one is less/greater than other).

Write test benches and simulate each module/submodule.

Hint: First make individual modules of the four-bit adder, four-bit subtractor, four-bit multiplier, four-bit comparator modules (make all these in same/one project) and then use a multiplexer to combine these modules to make an ALU where the user should select which operation he/she wants to perform (for instance, ALU may perform four-bit addition when selection lines are ‘00’using selection lines of a multiplexer or perform subtraction when selections lines are ‘01’ and so on).

The code should be simple as I am a beginner. Also, I need an urgent answer.

Answer 1

Verilog code for 4 bit addition:

main module program:

module 4bitadder(

input [3:0] a,b,

input cin,

output [3:0] sum,

output cout

);

wire c0,c1,c2;

fulladder1bit fa1(.a(a[0]),.b(b[0]),.cin(cin),.sum(sum[0]),.cout(c0));

fulladder1bit fa1(.a(a[1]),.b(b[1]),.cin(c0),.sum(sum[1]),.cout(c1));

fulladder1bit fa1(.a(a[2]),.b(b[2]),.cin(c1),.sum(sum[2]),.cout(c2));

fulladder1bit fa1(.a(a[3]),.b(b[3]),.cin(c2),.sum(sum[3]),.cout(cout));

end module

source module program:

module fulladder1bit(

input a,b,cin,

output sum,cout);

assign sum=a^b^cin;

assign cout=a&b | b&cin | cin&a;

end module

/*add this source file to main code while simulating*/

Verilog code for 4 bit subtraction:

main program:

module 4bitsubtractor (

input [3:0] a,b,

input cin,

output [3:0] sub,

output bout

);

wire c0,c1,c2;

fullsub1bit fs1(.a(a[0]),.b(b[0]),.cin(cin),.sub(sub[0]),.bout(c0));

fullsub1bit fs2(.a(a[1]),.b(b[1]),.cin(c0),.sub(sub[1]),.bout(c1));

fullsub1bit fs3(.a(a[2]),.b(b[2]),.cin(c1),.sub(sub[2]),.bout(c2));

fullsub1bit fs4(.a(a[3]),.b(b[3]),.cin(c2),.sub(sub[3]),.bout(bout));

end module

source module program:

module fullsub1bit(

input a,b,cin,

output sub,bout);

assign sub=a^b^cin;

assign bout=(~a*c) +(~a*b)+(b*c);

end module

Verilog code for 4 bit multiplication:

main program:

module 4bitmul(

input [3:0] Q,

input [3:0] M,

output [7:0] P

);

wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11;

wire d1,d2,d3,d4,d5,d6,d7;

wire e1,e2,e3;

wire f1,f2,f3,f4,f5,f6,f7;

wire g1,g2,g3,g4;

and(c1,M[3],Q[1]),

(c2,M[2],Q[2]),

(c3,M[1],Q[3]),

(c4,M[3],Q[0]),

(c5,M[2],Q[1]),

(c6,M[1],Q[2]),

(c7,M[2],Q[0]),

(c8,M[1],Q[1]),

(c9,M[0],Q[2]),

(c10,M[1],Q[0]),

(c11,M[0],Q[1]),

(P[0],M[0],Q[0]);

fulladder1bit fa1(.a(c1),.b(c20,.cin(c3),.sum(d2),.cout(d1));

fulladder1bit fa2(.a(c4),.b(c5),.cin(c6),.sum(d4),.cout(d3));

fulladder1bit fa3(.a(c7),.b(c8),.cin(c9),.sum(d6),.cout(d5));

fulladder1bit fa4(.a(c10),.b(c11),.cin(0),.sum(P[1]),.cout(d7));

and(e1,M[2],Q[3]),

(e2,M[3],Q[2]),

(e3,M[0],Q[3]);

fulladder1bit fa5(.a(e1),.b(e2),.cin(d1),.sum(f2),.cout(f1));

fulladder1bit fa6(.a(d2),.b(d3),.cin(f5),.sum(f4),.cout(f3));

fulladder1bit fa7(.a(d4),.b(e3),.cin(d5),.sum(f6),.cout(f5));

fulladder1bit fa8(.a(d6),.b(d7),.cin(0),.sum(P[2]),.cout(f7));

and(g1,M[3],Q[3]);

fulladder1bit fa9(.a(g1),.b(f1),.cin(g2),.sum(P[6]),.cout(P[7]));

fulladder1bit fa10(.a(f2),.b(f3),.cin(g3),.sum(P[5]),.cout(g2));

fulladder1bit fa11(.a(f4),.b(0),.cin(g4),.sum(P[4]),.cout(g3));

fulladder1bit fa12(.a(f6),.b(f7),.cin(0),.sum(P[3]),.cout(g4));

Endmodule

/* add full adder source module*/

Verilog code for 4 bit comparator:

Source program:

module 1bitcomparator(a,b,c,gt,eq,sm);

input a,b;

output reg eq, gt,sm;

always@(a,b)

begin

if(a==b)

{eq,gt,sm}=3'b100;

else if(a>b)

{eq,gt,sm}=3'b010;

else if(a<b)

{eq,gt,sm}=3'b001;

else

   {eq,gt,sm}=3'b000;

end module

Main program:

module 4bitcomparator(

input [3:0] a,b,

output [3:0] eq,gt,sm

);

1bitcomparator cp1(.a(a[0]),.b(b[0]),.eq(eq[0]),.gt(gt[0]),.sm(sm[0]));

1bitcomparator cp1(.a(a[1]),.b(b[1]),.eq(eq[1]),.gt(gt[1]),.sm(sm[1]));

1bitcomparator cp1(.a(a[2]),.b(b[2]),.eq(eq[2]),.gt(gt[2]),.sm(sm[2]));

1bitcomparator cp1(.a(a[3]),.b(b[3]),.eq(eq[3]),.gt(gt[3]),.sm(sm[3]));

end module

VERILOG CODE FOR 4 BIT ALU:

module mux(a,b,c,d,s1,s2,out);

input a,b,c,d,s1,s2;

output reg out;

always@(s1,s2)

begin

case ({s1,s2})

0:out=a;

  1:out=b;

2:out=c;

  3:out=d;   

default out=1'bx;

endcase

end

end module