Question

How does SPI indicate which slave device is being accessed ?

How does I2C indicate which slave device is being accessed ?

Answer 1

Ans1- Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards. It uses separate clock and data lines, along with a select line to choose the device you wish to talk to.

SPI devices communicate in full duplex mode using a master-slave architecture with a single master. The master device originates the frame for reading and writing. Multiple slave-devices are supported through selection with individual slave select (SS).

The SPI bus specifies four logic signals:

• SCLK: Serial Clock (output from master)
• MOSI: Master Output Slave Input, or Master Out Slave In (data output from master)
• MISO: Master Input Slave Output, or Master In Slave Out (data output from slave)
• SS: Slave Select (often active low, output from master)

MOSI (on a master) connects to MOSI (on a slave). MISO ( on a master) connects to MISO ( on a slave). Slave Select is the same functionality as chip-select and is used instead of an addressing concept. Pin names are always capitalized as in Slave Select, Serial Clock, and Master Output Slave Input.

If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it. Some slaves require a falling edge of the chip select signal to initiate an action. Slave Select tells the slave that it should wake up and receive / send data and is also used when multiple slaves are present to select the one you'd like to An example is the Maxim MAX1242 ADC, which starts conversion on a high→low transition. With multiple slave devices, an independent SS signal is required from the master for each slave device.Most slave devices have tri-state outputs so their MISO signal becomes high impedance (electrically disconnected) when the device is not selected.

To begin communication, the bus master configures the clock, using a frequency supported by the slave device, typically up to a few MHz. The master then selects the slave device with a logic level 0 on the select line. If a waiting period is required, such as for an analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles.

During each SPI clock cycle, a full-duplex data transmission occurs. The master sends a bit on the MOSI line and the slave reads it, while the slave sends a bit on the MISO line and the master reads it. This sequence is maintained even when only one-directional data transfer is intended.

Note that, for this layout, data overflows from one slave to the next, so to send data to any one slave, you'll need to transmit enough data to reach all of them. Also, keep in mind that the first piece of data you transmit will end up in the last slave.

Ans-2- The I 2C bus is a very popular and powerful bus used for communication between a master (or multiple masters) and a single or multiple slave devices.

I2C works with it's two wires, the SDA(data line) and SCL(clock line). Both these lines are open-drain, but are pulled-up with resistors. Usually there is one master and one or multiple slaves on the line, although there can be multiple masters. Both masters and slaves can transmit or receive data, therefore, a device can be in one of these four states: master transmit, master receive, slave transmit, slave receive.

The master initiates the communication by sending a START bit, this bit alerts all the slaves that some data is coming and they need to listen. After the start bit, 7 bits of a unique slave address is sent. Each slave has it's own slave address, this way, only one slave will respond to the data. The last sent bit is the read/write bit. If this bit is 0, it means that the master wishes to write data to a register of the slave, if this bit is 1, it means that the master wishes to read data from a register of a slave.

The general procedure for a master to access a slave device is the following:

1. Suppose a master wants to send data to a slave:

• Master-transmitter sends a START condition and addresses the slave-receiver

• Master-transmitter sends data to slave-receiver

• Master-transmitter terminates the transfer with a STOP condition

2. If a master wants to receive/read data from a slave:

• Master-receiver sends a START condition and addresses the slave-transmitter

• Master-receiver sends the requested register to read to slave-transmitter

• Master-receiver receives data from the slave-transmitter

• Master-receiver terminates the transfer with a STOP condition