Question

Why the CMOS logic is ratio less logic?

2. As a designer, you have asked to design a digital logic circuit in which the inverter is one of the main building blocks. For inverter design, you have to choose either depletion load NMOS inverter or saturated enhancement load inverter. Which of the inverter will you use in your design and why? Explain clearly?

3. Design of a 2 input XNOR gate using CMOS transistors,

a. Realize the 2 input XNOR gate using static CMOS transistor.

b. Draw the stick diagram of 2 input XNOR gate;

c. Apprpriate device sizing can result in equal and symmetrical drive current which leads to a sunstainable design. In order to obtained optimum operation of the ciruit determine the (?????)??,???? and (?????)??,???? for the 2 input XNOR gate. Assume that (?????)??=28 for all PMOS transistors and (?????)??=12 for all NMOS transistors.

Answer 1

1). CMOS logic has the pull up network and the pull down network which are complementary to each other. That means when the pull up network is active the pull down network is inactive. Since both the networks work independently, so there is no fight between the pull up network and pull down network to pull up or pull down the output node to VDD or GND respectively. So the cmos logic is ratioless logic.

2).As in the case of saturated enhancement load inverter the high level is VOH = VDD - VTload.

But in case of depletion load NMOS inverter the VOH = VDD.

So depletion load NMOS inverter has better noise margin.

3). 2 input XNOR gate.