Question

As a designer, you have asked to design a digital logic circuit in which the inverter is one of the main building blocks. For inverter design, you have to choose either depletion load NMOS inverter or saturated enhancement load inverter. Which of the inverter will you use in your design and why? Explain clearly?

VLSI

Answer 1

I will choose depletion load NMOS inverter for inverter design because we can have V_o = V_DD whereas in depletion NMOS inverter V_o is always less than V_DD.

When Gate ans source are connected V_GSL = 0.

Since the threshold voltage of load transistor is negative.

For cut off Mode , whe V_I < V_TND . Then no drain current flows in either transistors. That means the load transistor must be in the linear region of the operation and the output current can be expressed as fellows

v_DSL(sat) = V_GSL - V_TNL = - V_TNL

So, V_GSL = 0

i_DL(linear)=K_L/ [2(V_GSL - V_TNL)V_DSL - V_DSL²]

Since V_GSL=0, and i_DL=0

0=-K_L/ [2V_TNLV_DSL + V_DSL²] Which gives

V_o = V_DD