Question

CMOS Design Styles. Select the correct answer for each.

a) What do you expect to happen if you accidentally hook the Clk signal to the inverter input?

-Output will switch twice in each clk cycle

-Output will latch to logic 1

-The control input will be confused, resulting in an unknown logic output state

-The power supply may burn up because the unconnected signal line may touch Gnd

-The load capacitance will rise too high, preventing the output switching

b) In a dynamic logic gate, what is the Vout value prior to the Evaluate cycle?

-Logic 1

-Logic 0

-Z-state

-Undefined logic state

-Depends upon whether both pMOS and nMOS are in z-state or not

Answer 1

a)ouput will switch twice in each clock cycle.since for each clock cycle there is logic 0 and logic 1.

There will rise time and fall time in output switching.due to load capcitance at ouput.

Answer can be both first and last options.because if there is large capcitance at load it will take more time for charging and discharging . preventing the output to switching from logic 0 and logic 1

b)in dynamic logic gate , prior to evaluation cycle output is in undefined logic state.

In dynamic logic

Prcharge (clk=0) PMOS is on the entire vdd is used for charging capacitor.undefined logic appears at output.here output is independent of inputs

Evaluation (clk=1) nmos is on.during evaluation phase output bis set to logic 0, logic1.output is dependent on input combination.