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Write verilog code for a 8:1 Mux using the blocks of 2:1 Mux.

Write verilog code for a 8:1 Mux using the blocks of 2:1 Mux.

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Answer #1

FIRST LET UNDERSTAND AND SEE HOW THE BLOCK DIAGRAM WILL BE FOR 8:1 MUX USING 2:1MUX

VERILOG DESIGN CODE FOR 8:1 MUX USING 2:1 MUX

module mux8to1(d,sel,y);
input [7:0]d;
input [2:0]sel;
output y;

wire [3:0]w;
wire [1:0]a;
//mux numbers are marked in RED in block digram.
mux2to1 mux1 (d[1:0],sel[0],w[0]);
mux2to1 mux2 (d[3:2],sel[0],w[1]);
mux2to1 mux3 (d[5:4],sel[0],w[2]);
mux2to1 mux4 (d[7:6],sel[0],w[3]);

mux2to1 mux5 (w[1:0],sel[1],a[0]);
mux2to1 mux6 (w[3:2],sel[1],a[1]);

mux2to1 mux7 (a[1:0],sel[2],y);

endmodule

//BLOCK OF 2:1 MUX

//THIS MODULE IS INSTANTIATED IN UPPER MODULE TO GET 8:1 MUX
module mux2to1(i,s,f);
input i;
input s;
output f;

assign f=i[s];
endmodule

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