Question

(ii) Create a hierarchical Verilog 5-to-1 mux module with five data inputs (a, b, c, d, e), three select inputs (s[2:0]), and one output bit (f) using 4-to-1 multiplexers. Design the 4-to-1 multiplexer using behavioral code.

Answer #1

**Solution:-**

**Verilog Code for 4x1
MUX**

module mux4x1 (Data_in, Sel, Y);

input [3:0] Data_in; // Data input

input [1:0] Sel; // Select line input

output Y; // Output

assign Y = (!Sel[1] & !Sel[0] & Data_in[0]) | // When
Sel = "00" then Y = Data_in[0]

(!Sel[1] & Sel[0] & Data_in[1]) | // When Sel = "01" then Y
= Data_in[1]

( Sel[1] & !Sel[1] & Data_in[2]) | // When Sel = "10" then
Y = Data_in[2]

( Sel[0] & Sel[1] & Data_in[3]) ; // When Sel = "11" then Y
= Data_in[3]

endmodule

**Verilog Code
for 5x1 MUX using 4x1 MUX**

module mux5x1 (In1, S, Out1);

input [4:0] In1; // Data input

input [2:0] S; // Select line input

output Out1; // Output

// Internal wire connection

wire Y;

mux4x1 u_MUX (.Data_in(In1[3:0]), .Sel(S[1:0]), .Y(Y));

assign Out1 = S[2] ? In1[4] : Y;

endmodule

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