Question

write verilog code to generate a clock signal clk with 10 ns period

Answer 1

Time period of clock is 10ns. Half period of clock is 10ns/2=5ns,

we know that generally clk signal has two states, High and low, So provide 5ns delay to each state.

The verilog code is given below

module clk_10ns(clk);
output clk;
reg clk;
initial
    begin
      clk=0;//initialize the clk signal
      while(1)///infinite loop
        begin
          clk=(~clk);//toggle the previous state(i.e 0 to 1 or 1 to 0)
          #5; //5ns delay
        end
    end
endmodule

(If you have any query leave a comment, Thank you)